# US 12,008,239 B1 · Memory management method, memory storage device and memory control circuit unit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,008,239 B1 - Document ID: US12008239B1 - Status: Granted - Kind: B1 - Application number: 18/151,470 - Filed: 2023-01-09 - Published: 2024-06-06 - Granted: 2024-06-11 - Earliest claimed: 2022-12-02 - Assignees: Phison Electronics Corp. - Applicants: Phison Electronics Corp. - Inventors: Wei-Cheng Li; Ping-Cheng Chen; Yu-Chung Shen; Jia-Li Xu - Web page: https://patentgrep.com/patent/US12008239B1 ## CPC - G06F 3/061: {Improving I/O performance} - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit. ## Claims ### Claim 1 A memory management method, configured for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units, and the memory management method comprises: sending an erase command sequence, wherein the erase command sequence is configured to erase a first physical erasing unit in the plurality of physical erasing units; and sending a write command sequence with correspondence to the erasing of the first physical erasing unit, wherein the write command sequence is configured to perform a dummy write operation on a second physical erasing unit in the plurality of physical erasing units, and the dummy write operation is configured to store dummy data to the second physical erasing unit. ### Claim 2 (depends on 1) The memory management method of claim 1, further comprising: ignoring a write failure event corresponding to the dummy write operation after the dummy write operation is performed. ### Claim 3 (depends on 1) The memory management method of claim 1, wherein the dummy data is not mapped by any logical unit. ### Claim 4 (depends on 1) The memory management method of claim 1, wherein in the dummy write operation, the dummy data is stored in one physical programming unit in the second physical erasing unit. ### Claim 5 (depends on 1) The memory management method of claim 1, wherein the operation of sending the write command sequence with correspondence to the erasing of the first physical erasing unit comprises: temporarily storing identification information corresponding to the second physical erasing unit with correspondence to the erasing of the first physical erasing unit; and sending the write command sequence according to the identification information before a normal write operation is performed on the second physical erasing unit. ### Claim 6 (depends on 1) The memory management method of claim 1, wherein the second physical erasing unit comprises at least a portion of the plurality of physical erasing units not fully written. ### Claim 7 (depends on 1) The memory management method of claim 1, further comprising: reading identification information of at least one physical erasing unit associated with the first physical erasing unit from management information with correspondence to the erasing of the first physical erasing unit; and determining the second physical erasing unit from the plurality of physical erasing units according to the identification information. ### Claim 8 A memory storage device, comprising: a connection interface unit configured to be coupled to a host system; a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units; and a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to: send an erase command sequence, wherein the erase command sequence is configured to erase a first physical erasing unit in the plurality of physical erasing units; and send a write command sequence with correspondence to the erasing of the first physical erasing unit, wherein the write command sequence is configured to perform a dummy write operation on a second physical erasing unit in the plurality of physical erasing units, and the dummy write operation is configured to store dummy data to the second physical erasing unit. ### Claim 9 (depends on 8) The memory storage device of claim 8, wherein the memory control circuit unit is further configured to: ignore a write failure event corresponding to the dummy write operation after the dummy write operation is performed. ### Claim 10 (depends on 8) The memory storage device of claim 8, wherein the dummy data is not mapped by any logical unit. ### Claim 11 (depends on 8) The memory storage device of claim 8, wherein in the dummy write operation, the dummy data is stored in one physical programming unit in the second physical erasing unit. ### Claim 12 (depends on 8) The memory storage device of claim 8, wherein the operation of the memory control circuit unit sending the write command sequence with correspondence to the erasing of the first physical erasing unit comprises: temporarily storing identification information corresponding to the second physical erasing unit with correspondence to the erasing of the first physical erasing unit; and sending the write command sequence according to the identification information before a normal write operation is performed on the second physical erasing unit. ### Claim 13 (depends on 8) The memory storage device of claim 8, wherein the second physical erasing unit comprises at least a portion of the plurality of physical erasing units not fully written. ### Claim 14 (depends on 8) The memory storage device of claim 8, wherein the memory control circuit unit is further configured to: read identification information of at least one physical erasing unit associated with the first physical erasing unit from management information with correspondence to the erasing of the first physical erasing unit; and determine the second physical erasing unit from the plurality of physical erasing units according to the identification information. ### Claim 15 A memory control circuit unit, configured to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units, and the memory control circuit unit comprises: a host interface configured to be coupled to a host system; a memory interface configured to be coupled to the rewritable non-volatile memory module; and a memory management circuit coupled to the host interface and the memory interface, wherein the memory management circuit is configured to: send an erase command sequence, wherein the erase command sequence is configured to erase a first physical erasing unit in the plurality of physical erasing units; and send a write command sequence with correspondence to the erasing of the first physical erasing unit, wherein the write command sequence is configured to perform a dummy write operation on a second physical erasing unit in the plurality of physical erasing units, and the dummy write operation is configured to store dummy data to the second physical erasing unit. ### Claim 16 (depends on 15) The memory control circuit unit of claim 15, wherein the memory management circuit is further configured to: ignore a write failure event corresponding to the dummy write operation after the dummy write operation is performed. ### Claim 17 (depends on 15) The memory control circuit unit of claim 15, wherein the dummy data is not mapped by any logical unit. ### Claim 18 (depends on 15) The memory control circuit unit of claim 15, wherein in the dummy write operation, the dummy data is stored in one physical programming unit in the second physical erasing unit. ### Claim 19 (depends on 15) The memory control circuit unit of claim 15, wherein the operation of the memory management circuit sending the write command sequence with correspondence to the erasing of the first physical erasing unit comprises: temporarily storing identification information corresponding to the second physical erasing unit with correspondence to the erasing of the first physical erasing unit; and sending the write command sequence according to the identification information before a normal write operation is performed on the second physical erasing unit. ### Claim 20 (depends on 15) The memory control circuit unit of claim 15, wherein the second physical erasing unit comprises at least a portion of the plurality of physical erasing units not fully written. ### Claim 21 (depends on 15) The memory control circuit unit of claim 15, wherein the memory management circuit is further configured to: read identification information of at least one physical erasing unit associated with the first physical erasing unit from management information with correspondence to the erasing of the first physical erasing unit; and determine the second physical erasing unit from the plurality of physical erasing units according to the identification information.