# US 12,008,237 B2 · Memory bit cell with homogeneous layout pattern of base layers for high density memory macros

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- Number: US 12,008,237 B2
- Document ID: US12008237B2
- Status: Granted
- Kind: B2
- Application number: 17/724,123
- Filed: 2022-04-19
- Published: 2023-10-19
- Granted: 2024-06-11
- Earliest claimed: 2022-04-19
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: Kurt M. English; Charwak Suresh Apte
- Web page: https://patentgrep.com/patent/US12008237B2

## CPC

- G06F 3/061: {Improving I/O performance}
- G11C 11/418: Address circuits
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 8/16: Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
- H10B 10/12: {comprising a MOSFET load element}
- G11C 11/419: Read-write [R-W] circuits
- H10D 89/10: Integrated device layouts
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An apparatus and method for designing memory macro blocks. A memory includes one or more memory banks, each with one or more arrays and input/output (I/O) blocks used to perform read accesses and write accesses. An array that utilizes multiple memory bit cells, and the I/O blocks are placed in a manner that they are abutting one another. The layout of the memory bit cells and the I/O blocks use a same subset of parameters of a semiconductor fabrication process. As a result, the memory bank does not include the placement of any boundary cells, which are used to improve yield of semiconductor layout. By skipping the use of the boundary cells, the dimensions of the memory bank are reduced, and layout density increases. Additionally, the memory bit cells use one or more p-type devices for one or more read pass gates.

## Claims

### Claim 1

A circuit comprising:
an array of memory bit cells for storing data arranged as a plurality of rows and a plurality of columns; and
first input/output (I/O) block abutting a first side of the array of memory bit cells; and
wherein:
each of the array of memory bit cells and the first I/O block includes base layers with a first subset of parameters of a semiconductor fabrication process, wherein the base layers are layers between a silicon substrate layer and a signal interconnect metal layer closest to the silicon substrate layer; and
in response to receiving, from the first I/O block, an indication of a read operation targeting a given row of the plurality of rows comprising a first memory bit cell, the array of memory bit cells is configured to convey first data stored in the first memory bit cell.

### Claim 2 (depends on 1)

The circuit as recited in claim 1, wherein the first subset of parameters comprises a repeatable pattern of one or more p-type diffusion regions and one or more n-type diffusion regions used to define active regions of a plurality of standard cells in a standard cell library.

### Claim 3 (depends on 2)

The circuit as recited in claim 2, wherein the repeatable pattern comprises a given width for each of the one or more p-type diffusion regions and one or more n-type diffusion regions allowing a same number of Fins to be formed over one or more memory bit cells of the array and one or more cells of the first I/O block.

### Claim 4 (depends on 1)

The circuit as recited in claim 1, wherein read access circuitry of the first memory bit cell comprises only p-type transistors.

### Claim 5 (depends on 4)

The circuit as recited in claim 4, wherein a number of contacted gate pitches (CPP) of the first memory bit cell is four.

### Claim 6 (depends on 1)

The circuit as recited in claim 1, further comprising a second I/O block abutting a second side of the array of memory bit cells different from the first side, wherein the second I/O block:
is configured to receive the first data stored in the first memory bit cell; and
comprises the first subset of parameters.

### Claim 7 (depends on 1)

The circuit as recited in claim 1, wherein write access circuitry of the first memory bit cell comprises n-type transistors with a first threshold voltage less than a second threshold voltage of p-type transistors of data storage circuitry of the first memory bit cell.

### Claim 8

A method comprising:
storing data in an array of memory bit cells arranged as a plurality of rows and a plurality of columns with a first input/output (I/O) block abutting a first side of the array of memory bit cells; and
wherein:
each of the array of memory bit cells and the first I/O block includes base layers with a first subset of parameters of a semiconductor fabrication process, wherein the base layers are layers between a silicon substrate layer and a signal interconnect metal layer closest to the silicon substrate layer; and
in response to receiving, from the first I/O block, an indication of a read operation targeting a given row of the plurality of rows comprising a first memory bit cell, conveying, by the array of memory bit cells, first data stored in the first memory bit cell.

### Claim 9 (depends on 8)

The method as recited in claim 8, wherein the first subset of parameters comprises a repeatable pattern of one or more p-type diffusion regions and one or more n-type diffusion regions used to define active regions of a plurality of standard cells in a standard cell library.

### Claim 10 (depends on 9)

The method as recited in claim 9, wherein the repeatable pattern comprises a given width for each of the one or more p-type diffusion regions and one or more n-type diffusion regions allowing a same number of Fins to be formed over one or more memory bit cells of the array and one or more cells of the first I/O block.

### Claim 11 (depends on 8)

The method as recited in claim 8, wherein read access circuitry of the first memory bit cell comprises only p-type transistors.

### Claim 12 (depends on 11)

The method as recited in claim 11, wherein a number of contacted gate pitches (CPP) of the first memory bit cell is four.

### Claim 13 (depends on 9)

The method as recited in claim 9, further comprising receiving the first data stored in the first memory bit cell by a second I/O block abutting a second side of the array of memory bit cells different from the first side, wherein the second I/O block comprises the first repeatable pattern of one or more p-type diffusion regions and one or more n-type diffusion regions.

### Claim 14 (depends on 8)

The method as recited in claim 8, wherein write access circuitry of the first memory bit cell comprises n-type transistors with a first threshold voltage less than a second threshold voltage of p-type transistors of data storage circuitry of the first memory bit cell.

### Claim 15

A computing system comprising
a memory configured to store instructions of one or more tasks and source data to be processed by the one or more tasks; and
an integrated circuit configured to execute the instructions using the source data, wherein the integrated circuit comprises:
an array of memory bit cells for storing data arranged as a plurality of rows and a plurality of columns; and
first input/output (I/O) block abutting a first side of the array of memory bit cells; and
wherein:
each of the array of memory bit cells and the first I/O block includes base layers with a first subset of parameters of a semiconductor fabrication process, wherein the base layers are layers between a silicon substrate layer and a signal interconnect metal layer closest to the silicon substrate layer; and
in response to receiving, from the first I/O block, an indication of a read operation targeting a given row of the plurality of rows comprising a first memory bit cell, the array of memory bit cells is configured to convey first data stored in the first memory bit cell.

### Claim 16 (depends on 15)

The computing system as recited in claim 15, wherein the first subset of parameters comprises a repeatable pattern of one or more p-type diffusion regions and one or more n-type diffusion regions used to define active regions of a plurality of standard cells in a standard cell library.

### Claim 17 (depends on 16)

The computing system as recited in claim 16, wherein the repeatable pattern comprises a given width for each of the one or more p-type diffusion regions and one or more n-type diffusion regions allowing a same number of fins to be formed over one or more memory bit cells of the array and one or more cells of the first I/O block.

### Claim 18 (depends on 15)

The computing system as recited in claim 15, wherein read access circuitry of the first memory bit cell comprises only p-type transistors.

### Claim 19 (depends on 18)

The computing system as recited in claim 18, wherein a number of contacted gate pitches (CPP) of the first memory bit cell is four.

### Claim 20 (depends on 16)

The computing system as recited in claim 16, wherein the integrated circuit further comprises a second I/O block abutting a second side of the array of memory bit cells different from the first side, wherein the second I/O block:
is configured to receive the first data stored in the first memory bit cell; and
comprises the repeatable pattern of one or more p-type diffusion regions and one or more n-type diffusion regions.