# US 12,008,236 B2 · Tuned datapath in stacked memory device

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- Number: US 12,008,236 B2
- Document ID: US12008236B2
- Status: Granted
- Kind: B2
- Application number: 17/461,035
- Filed: 2021-08-30
- Published: 2023-03-02
- Granted: 2024-06-11
- Earliest claimed: 2021-08-30
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Hari Giduturi; Bret Addison Johnson
- Web page: https://patentgrep.com/patent/US12008236B2

## CPC

- G06F 3/061: {Improving I/O performance}
- G11C 29/023: {in clock generator or timing circuitry}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/1201: {comprising I/O circuitry}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 29/12015: {comprising clock generation or timing circuitry}
- G11C 29/46: Test trigger logic
- G11C 2207/2254: Calibration
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A device includes a first memory die and a second memory die directly coupled to the first memory die via a first bus. The device also includes a second bus directly coupled to the first memory die. The first memory die includes a first trim circuit that when in operation adjusts a delay of signal transmission by the first memory die to a first value, while the second memory die comprises a second trim circuit that when in operation adjusts a delay of signal transmission by the second memory die to a second value.

## Claims

### Claim 1

A device, comprising:
a first memory die;
a second memory die directly coupled to the first memory die via a first bus; and
a second bus directly coupled to the first memory die and indirectly coupled to the second memory die, wherein the first memory die comprises a first trim circuit that when in operation adjusts a delay of signal transmission by the first memory die to a first value, wherein the second memory die comprises a second trim circuit that when in operation adjusts a delay of signal transmission by the second memory die to a second value, wherein the first memory die comprises a self tuning circuit that when in operation controls configuration of the second trim circuit of the second memory die.

### Claim 2 (depends on 1)

The device of claim 1, wherein device comprises a third memory die directly coupled to the second memory die via the first bus.

### Claim 3 (depends on 2)

The device of claim 2, wherein the third memory die is disposed on the second memory die and wherein the second memory die is disposed on the first memory die to form a memory stack.

### Claim 4 (depends on 1)

The device of claim 1, wherein the second bus is coupled to a host device.

### Claim 5 (depends on 4)

The device of claim 4, wherein the first memory die when in operation receives at least one signal from the host device via the second bus.

### Claim 6 (depends on 5)

The device of claim 5, wherein the first memory die when in operation transmits the at least one signal to the second memory die via the first bus.

### Claim 7 (depends on 6)

The device of claim 6, wherein the first memory die when in operation receives at least one second signal from the second memory die via the first bus.

### Claim 8 (depends on 7)

The device of claim 7, wherein the first memory die when in operation transmits the at least one second signal to the host device via the second bus.

### Claim 9 (depends on 1)

The device of claim 1, wherein the first value and an amount of time to complete a memory operation by the first memory die combine to be a net timing delay value.

### Claim 10 (depends on 9)

The device of claim 9, wherein the second value and a second amount of time to complete the memory operation by the second memory die combine to be the net timing delay value.

### Claim 11 (depends on 1)

The device of claim 1, wherein the self tuning circuit of the first memory die when in operation controls initialization of the first trim circuit.

### Claim 12

A method, comprising:
initiating a memory operation at a first memory die of a memory stack via a front end interface path directly coupled to the first memory die;
determining a first amount of time to complete the memory operation;
initiating the memory operation at a second memory die of the memory stack via the front end interface path indirectly coupled to the second memory die;
determining a second amount of time to complete the memory operation;
calibrating a first delay circuit of the first memory die to generate a first signal transmission delay in the first memory die when the first amount of time is less than the second amount of time; and
calibrating a second delay circuit of the second memory die via a self tuning circuit disposed in the first memory die to generate a second signal transmission delay in the second memory die when the first amount of time is greater than the second amount of time.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first signal transmission delay in the first memory die is a user determined first value, wherein the second signal transmission delay in the second memory die is a user determined second value.

### Claim 14 (depends on 12)

The method of claim 12, comprising automatically determining the first signal transmission delay in the first memory die and automatically determining the second signal transmission delay in the second memory die.

### Claim 15 (depends on 12)

The method of claim 12, comprising calibrating the first delay circuit during manufacture of a package comprising the first memory die and calibrating the second delay circuit during the manufacture of the package comprising the second memory die.

### Claim 16 (depends on 12)

The method of claim 12, comprising calibrating the first delay circuit and the second delay circuit at power up of a device comprising the first memory die and the second memory die.

### Claim 17

A device, comprising:
a first memory die comprising a first trim circuit that when in operation delays transmission of a signal by the first memory die by a first fixed amount, wherein the first memory die when in operation receives first operational signals from an external host directly coupled to the first memory die via a front end interface path; and
a second memory die disposed directly on the first memory die, wherein the second memory die when in operation receives second operational signals indirectly from the external host via a direct coupling between the first memory die and the second die, wherein the direct coupling between the first memory die and the second die is separate from the front end interface path directly coupling the first memory die and the external host, wherein the second memory die comprises a second trim circuit that when in operation delays transmission of a second signal by the second memory die by a second fixed amount, wherein the first fixed amount and the second fixed amount equalize an amount of time used by the first memory die and the second memory die to complete a memory operation, wherein the first memory die comprises a self tuning circuit that when in operation calibrates the first trim circuit to delay transmission of the signal by the first memory die by the first fixed amount and when in operation calibrates the second trim circuit to delay transmission of the second signal by the second memory die by the second fixed amount.

### Claim 18 (depends on 17)

The device of claim 17, wherein the first memory die when in operation transmits at least one signal, received from the external host, to the second memory die via a bus interconnecting the first memory die and the second memory die.