# US 12,008,234 B2 · Managing memory in an electronic system

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- Number: US 12,008,234 B2
- Document ID: US12008234B2
- Status: Granted
- Kind: B2
- Application number: 17/523,175
- Filed: 2021-11-10
- Published: 2023-05-11
- Granted: 2024-06-11
- Earliest claimed: 2021-11-10
- Assignees: Teradyne, Inc.
- Applicants: Teradyne, Inc.
- Inventors: Scott D. Schaber; Howard Lin
- Web page: https://patentgrep.com/patent/US12008234B2

## CPC

- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 11/263: Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers}
- G06F 11/2635: {using a storage for the test inputs, e.g. test ROM, script files}
- G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)}
- G06F 12/0638: {Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70)}
- G11C 29/56: External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C 29/56012: {Timing aspects, clock generation, synchronisation}
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/1024: Latency reduction
- G06F 2212/1056: Simplification
- G11C 2029/5602: {Interface to device under test}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An example system includes first memory, second memory having a greater areal density than the first memory, and a logic circuit configured to move some test data from the second memory to the first memory while at least one of (i) reading other test data from the first memory or (ii) processing the other test data. The logic circuit is configured to process the other test data prior to output along a test channel. The test channel leads to a device under test (DUT) to be tested.

## Claims

### Claim 1

A system comprising:
first memory;
second memory having a greater storage capacity than the first memory; and
a logic circuit configured to move test data from the second memory to the first memory while (i) reading other test data from the first memory, or (ii) both reading the other test data and processing the other test data, the logic circuit being configured to process the other test data prior to output along a test channel, where the test channel leads to a device under test (DUT) to be tested;
wherein the first memory comprises a first memory module and a second memory module; and
wherein moving the test data from the second memory to the first memory comprises reading the test data from the second memory and storing the test data, in the first memory module while reading the other test data from the second memory module.

### Claim 2 (depends on 1)

The system of claim 1, wherein moving the test data from the second memory to the first memory comprises reading the test data from the second memory and storing the test data in the first memory module while processing the other test data.

### Claim 3 (depends on 1)

The system of claim 1, wherein processing the other test data comprises setting timing for the other test data and performing at least one of branching, looping, or jumping operations in a script operating on the other test data.

### Claim 4 (depends on 1)

The system of claim 1, wherein the system comprises a test system, the test system further comprising:
pin electronics along the test channel, the pin electronics being configured to receive the other test data following processing by the logic circuit and to output testing data to the DUT that is based on the other test data.

### Claim 5

A system comprising:
first memory;
second memory having a greater storage capacity than the first memory; and
a logic circuit configured to move test data from the second memory to the first memory while (i) reading other test data from the first memory, (ii) processing the other test data, or (iii) both reading the other test data and processing the other test data, the logic circuit being configured to process the other test data prior to output along a test channel, where the test channel leads to a device under test (DUT) to be tested;
wherein the first memory stores expect data, the expect data representing expected DUT test results; and
wherein the logic circuit is configured to receive test result data associated with the DUT, to read the expect data from the first memory, to compare the test result data to the expect data to identify whether the DUT has passed or failed testing, and to store in memory information for the DUT based on comparing the test result data to the expect data.

### Claim 6 (depends on 5)

The system of claim 5, wherein the first memory comprises a first double data rate dynamic random access memory (DDR RAM) and a second DDR RAM.

### Claim 7 (depends on 6)

The system of claim 6, wherein the second memory comprises stacked flash memory.

### Claim 8 (depends on 6)

The system of claim 6, wherein the second memory comprises network storage.

### Claim 9 (depends on 5)

The system of claim 5, wherein the information is stored in a log in the first memory; and
wherein the logic circuit is configured to move at least part of the log from the first memory to the second memory.

### Claim 10

A system comprising:
first memory;
second memory having a greater areal density than the first memory; and
a logic circuit configured to perform operations comprising:
reading first data from the second memory;
storing the first data in the first memory;
reading the first data from the first memory;
processing the first data prior to output to a test channel, where the test channel leads to a device under test (DUT) to be tested; and
while reading the first data from the first memory or while processing the first data: (i) reading second data from the second memory, and (ii) storing the second data in available first memory;
wherein the first data and the second data comprise test data;
wherein the first memory comprises a first memory module and a second memory module;
wherein storing the first data in the first memory comprises storing the first data in the first memory module;
wherein reading the first data from the first memory comprises reading the first data from the first memory module; and
wherein storing the second data in available first memory comprises storing the second data in the second memory module, the second memory module comprising the available first memory.

### Claim 11 (depends on 10)

The system of claim 10, wherein the operations comprise:
after all or part of the first data has been read from the first memory module, reading the second data from the second memory module and processing the second data prior to output to the test channel.

### Claim 12 (depends on 11)

The system of claim 11, wherein the operations comprise:
while the second data is being read from the second memory module or being processed:
reading third data from the second memory; and
storing the third data in the first memory module, the third data comprising test data.

### Claim 13 (depends on 12)

The system of claim 12, wherein the operations comprise:
after all or part of the second data has been read from the second memory module, reading the third data from the first memory module and processing the third data prior to output to the test channel.

### Claim 14 (depends on 10)

The system of claim 10, wherein the system comprises a test system, the test system further comprising:
pin electronics on the test channel, the pin electronics being configured to receive the first data following processing by the logic circuit, and to output testing data to the DUT that is based on the first data.

### Claim 15

A system comprising:
first memory;
second memory having a greater areal density than the first memory; and
a logic circuit configured to perform operations comprising:
reading first data from the second memory;
storing the first data in the first memory;
reading the first data from the first memory;
processing the first data prior to output to a test channel, where the test channel leads to a device under test (DUT) to be tested; and
while reading the first data from the first memory or while processing the first data: (i) reading second data from the second memory, and (ii) storing the second data in available first memory;
wherein the first data and the second data comprise test data;
wherein the first memory stores expect data, the expect data representing expected DUT test results; and
wherein the operations further comprise:
receiving test result data for the DUT;
reading the expect data from the first memory;
comparing the test result data to the expect data to identify whether the DUT passed or failed testing; and
storing, in the first memory, information for the DUT based on comparing the test result data to the expect data.

### Claim 16 (depends on 15)

The system of claim 15, wherein the first memory comprises a first double data rate dynamic random access memory (DDR RAM) and a second DDR RAM.

### Claim 17 (depends on 16)

The system of claim 16, wherein the second memory comprises stacked flash memory.

### Claim 18 (depends on 16)

The system of claim 16, wherein the second memory comprises network storage.

### Claim 19 (depends on 15)

The system of claim 15, wherein the processing first data comprises setting timing for the first data and performing at least one of branching, looping, or jumping operations in a script operating on the first data.

### Claim 20 (depends on 15)

The system of claim 15, wherein the information is stored in a log in the first memory;
wherein the operations further comprise moving at least part of the log from the first memory to the second memory; and
wherein the test data comprises test, vectors or test patterns to send to the DUT to test the DUT.

### Claim 21

One or more non-transitory machine-readable devices storing instructions that are executable by one or more processing devices to perform operations in a system that comprises first memory and second memory having a greater areal density than the first memory, the operations comprising:
reading first data from the second memory;
storing the first data in the first memory;
reading the first data from the first memory;
processing the first data prior to output to a test channel, where the test channel leads to a device under test (DUT) to be tested; and
while reading the first data read from the first memory or while processing the first data: (i) reading second data from the second memory, and (ii) storing the second data in available first memory;
wherein the first data and the second data comprise test data;
wherein the first memory stores expect data, the expect data representing expected DUT test results; and
wherein the operations further comprise:
receiving test result data for the DUT;
reading the expect data from the first memory;
comparing the test result data to the expect data to identify whether the DUT has passed or failed testing; and
storing, in the first memory, information for the DUT based on comparing the test result data to the expect data.

### Claim 22

A test system comprising:
first memory;
second memory having a greater storage capacity than the first memory and having a greater latency that the first memory; and
a logic circuit configured to store test data in the second memory and configured to copy at least part of the test data stored in the second memory into the first memory for execution by one or more processing devices, the test data comprising test vectors for testing a device under test (DUT);
wherein the first memory stores expect data, the expect data representing expected DUT test results; and
wherein the logic circuit is configured to receive test result data associated with the DUT, to read the expect data from the first memory, to compare the test result data to the expect data to identify whether the DUT has passed or failed testing, and to store in memory information for the DUT based on comparing the test result data to the expect data.

### Claim 23 (depends on 22)

The test system of claim 22, wherein the first memory comprises dynamic random access memory and the second memory comprises FLASH memory.

### Claim 24 (depends on 22)

The test system of claim 22, wherein the first memory comprises multiple memory modules.

### Claim 25 (depends on 22)

The test system of claim 22, wherein the logic circuitry is configured to copy the at least part of the test data stored in the second memory into the first memory based on availability of storage in the first memory.

### Claim 26

A test system comprising:
first memory;
second memory having a greater storage capacity than the first memory and having a greater latency that, the first memory; and
a logic circuit configured to store test data in the second memory and configured to copy at least a first part of the test data stored in the second memory into the first memory for execution by one or more processing devices, the test data comprising test vectors for testing a device;
wherein the second memory comprises one terabyte (TB) or more of storage and the first memory comprises 32 gigabytes or less of storage.