# US 12,008,068 B2 · In memory matrix multiplication and its usage in neural networks

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- Number: US 12,008,068 B2
- Document ID: US12008068B2
- Status: Granted
- Kind: B2
- Application number: 18/354,679
- Filed: 2023-07-19
- Published: 2023-11-09
- Granted: 2024-06-11
- Earliest claimed: 2016-03-23
- Assignees: GSI Technology, Inc.
- Applicants: GSI Technology Inc.
- Inventors: Avidan Akerib; Pat Lasserre
- Web page: https://patentgrep.com/patent/US12008068B2

## CPC

- G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0644: {Management of space entities, e.g. partitions, extents, pools}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/067: {Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]}
- G06N 3/04: Architecture, e.g. interconnection topology
- G06N 3/0499: Feedforward networks
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 15/00: Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G06N 3/063: using electronic means
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 8/10: Decoders
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A device for in memory vector-matrix multiplication includes a memory array and in-memory logic. The memory array has at least two sections and stores a multiplier matrix. The memory array also receives and stores an input multiplicand arranged in a vector such that the operands of the vector-matrix multiplication are located on a same column of the memory array. Each of the sections is one of: a volatile memory array, a non-volatile memory array, a destructive memory array and a non-destructive memory array. The in-memory logic computes an output of the vector-matrix multiplication using the stored input vector and the stored multiplier matrix. The memory array is one of the following type of memory array: RAM, DRAM, SRAM, Re-RAM, ZRAM, MRAM and Memristor.

## Claims

### Claim 1

A method for in memory vector-matrix multiplication, the method comprising:
having a multiplier matrix stored in a memory array having at least two sections, wherein each of said at least two sections is one of: a volatile memory array, a non-volatile memory array, a destructive memory array and a non-destructive memory array;
receiving an input multiplicand arranged in a vector and storing it in said memory array such that the operands of said vector-matrix multiplication are located on a same column of said memory array; and
in-memory, computing said vector-matrix multiplication using said stored input vector and said stored multiplier matrix.

### Claim 2

A device for in memory vector-matrix multiplication, the device comprising:
a memory array having at least two sections, said memory array storing a multiplier matrix, said memory array also to receive and store an input multiplicand arranged in a vector such that the operands of said vector-matrix multiplication are located on a same column of said memory array, wherein each of said at least two sections is one of: a volatile memory array, a non-volatile memory array, a destructive memory array and a non-destructive memory array; and
in-memory logic for computing an output of said vector-matrix multiplication using said stored input vector and said stored multiplier matrix.

### Claim 3 (depends on 2)

The device according to claim 2 and wherein said memory array is one of the following type of memory array: RAM, DRAM, SRAM, Re-RAM, ZRAM, MRAM and Memristor.

### Claim 4 (depends on 2)

The device according to claim 2 and wherein said multiplier matrix comprises weights of a neural network and wherein said input multiplicand is an input of said neural network.