# US 12,007,938 B2 · Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width

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- Number: US 12,007,938 B2
- Document ID: US12007938B2
- Status: Granted
- Kind: B2
- Application number: 17/827,882
- Filed: 2022-05-30
- Published: 2022-12-22
- Granted: 2024-06-11
- Earliest claimed: 2016-04-02
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Vedvyas Shanbhogue; Stephen J. Robinson; Christopher D. Bryant; Jason W. Brandt
- Web page: https://patentgrep.com/patent/US12007938B2

## CPC

- G06F 15/8007: {single instruction multiple data [SIMD] multiprocessors}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/3004: {to perform operations on memory}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30112: {comprising data of variable length}
- G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]}
- G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

## Claims

### Claim 1

A processor comprising:
a plurality of caches;
decode circuitry to decode an instruction, the instruction to provide information to address a source memory location and to provide information to address a destination memory location;
execution circuitry coupled with the decode circuitry, the execution circuitry to perform operations corresponding to the instruction, including to atomically store first data, including data loaded from the source memory location, to the destination memory location; and
a status register coupled with the execution circuitry, wherein status information is to be stored in a bit of the status register, the status information indicative of whether the first data has been stored to the destination memory location.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the status information is indicative of whether the first data has been accepted by a device.

### Claim 3 (depends on 1)

The processor of claim 1, wherein the status information is to be stored based on receipt of a response related to the atomic store of the first data to the destination memory location.

### Claim 4 (depends on 1)

The processor of claim 1, wherein the destination memory location corresponds to a work submission queue for a device.

### Claim 5 (depends on 4)

The processor of claim 4, wherein the work submission queue is a shared work submission queue.

### Claim 6 (depends on 4)

The processor of claim 4, wherein the work submission queue is a memory-mapped input-output (MMIO) shared work queue register.

### Claim 7 (depends on 4)

The processor of claim 4, wherein the first data is used to assign work to the device.

### Claim 8 (depends on 4)

The processor of claim 4, wherein the device is a storage controller.

### Claim 9 (depends on 1)

The processor of claim 1, wherein the instruction is a work submission instruction to submit work to a device.

### Claim 10 (depends on 1)

The processor of claim 1, wherein the destination memory location is in a memory-mapped input-output (MMIO) range.

### Claim 11 (depends on 1)

The processor of claim 1, wherein the first data is to bypass the plurality of caches irrespective of a memory type of the destination memory location.

### Claim 12 (depends on 1)

The processor of claim 1, wherein successful completion of the atomic store requires the destination memory location to be 64-byte aligned.

### Claim 13 (depends on 1)

The processor of claim 1, wherein the execution circuitry is to prevent data of a store younger than the instruction from merging with the first data.

### Claim 14 (depends on 1)

The processor of claim 1, wherein the instruction, to provide the information to address the destination memory location, is to specify a general-purpose register that is to have address information that is to be combined with address information from a segment register.

### Claim 15 (depends on 1)

The processor of claim 1, wherein the first data is 512-bits.

### Claim 16 (depends on 1)

The processor of claim 1, wherein the first data is 256-bits.

### Claim 17

A processor comprising:
a plurality of caches;
decode circuitry to decode an instruction to submit work to a device, the instruction to provide information to address a source memory location and to provide information to address a location in a memory-mapped input-output (MMIO) work submission queue for the device; and
execution circuitry coupled with the decode circuitry, the execution circuitry to perform operations corresponding to the instruction, including to atomically store first data, including data loaded from the source memory location, to the location in the MMIO work submission queue for the device to assign work to the device.

### Claim 18 (depends on 17)

The processor of claim 17, wherein the MMIO work submission queue is a shared MMIO work submission queue.

### Claim 19 (depends on 17)

The processor of claim 17, wherein the first data is to bypass the plurality of caches irrespective of a memory type of the location in the MMIO work submission queue.

### Claim 20 (depends on 17)

The processor of claim 17, wherein successful completion of the atomic store requires the location in the MMIO work submission queue to be 64-byte aligned.

### Claim 21 (depends on 17)

The processor of claim 17, wherein the execution circuitry is to prevent data of a store younger than the instruction from merging with the first data.

### Claim 22 (depends on 17)

The processor of claim 17, wherein the device is an accelerator device.

### Claim 23 (depends on 17)

The processor of claim 17, further comprising a status register coupled with the execution circuitry, wherein status information is to be stored in a bit of the status register, the status information indicative of whether the first data has been stored to the location in the MMIO work submission queue.

### Claim 24 (depends on 23)

The processor of claim 23, wherein the status information is indicative of whether the first data has been accepted by the device.

### Claim 25 (depends on 23)

The processor of claim 23, wherein the device is to store the status information in the bit of the status register.

### Claim 26 (depends on 17)

The processor of claim 17, wherein the instruction, to provide the information to address the location in the MMIO work submission queue, is to specify a general-purpose register that is to have address information that is to be combined with address information from a segment register.

### Claim 27 (depends on 17)

The processor of claim 17, wherein the first data is 512-bits.

### Claim 28 (depends on 17)

The processor of claim 17, wherein the first data is 256-bits.

### Claim 29 (depends on 17)

The processor of claim 17, wherein the device is a storage controller.

### Claim 30

An apparatus comprising:
an accelerator device; and
a processor coupled with the accelerator device, the processor comprising:
a plurality of caches;
decode circuitry to decode an instruction, the instruction to provide information to address a source memory location and to provide information to address a destination memory location;
execution circuitry coupled with the decode circuitry, the execution circuitry to perform operations corresponding to the instruction, including to atomically store first data, including data loaded from the source memory location, to the destination memory location; and
a status register coupled with the execution circuitry, wherein status information is to be stored in a bit of the status register, the status information indicative of whether the first data has been stored to the destination memory location.

### Claim 31 (depends on 30)

The apparatus of claim 30, wherein the status information is indicative of whether the first data has been accepted by the accelerator device.

### Claim 32 (depends on 30)

The apparatus of claim 30, wherein the status information is to be stored based on receipt of a response related to the atomic store of the first data to the destination memory location.

### Claim 33 (depends on 30)

The apparatus of claim 30, wherein the destination memory location corresponds to a memory-mapped input-output (MMIO) shared work submission queue for the accelerator device, and wherein the first data is used to assign work to the accelerator device.

### Claim 34 (depends on 30)

The apparatus of claim 30, wherein the first data is to bypass the plurality of caches irrespective of a memory type of the destination memory location, wherein successful completion of the atomic store requires the destination memory location to be 64-byte aligned, and wherein the execution circuitry is to prevent data of a store younger than the instruction from merging with the first data.

### Claim 35

A processor comprising:
a plurality of caches;
fetch circuitry to fetch an atomic store to memory instruction;
decode circuitry coupled with the fetch circuitry, the decode circuitry to decode the atomic store to memory instruction, the atomic store to memory instruction having a field to specify a 64-bit register, wherein the 64-bit register is a first of eight sequential 64-bit registers, the eight sequential 64-bit registers to collectively store a 512-bit data; and
execution circuitry coupled with the decode circuitry, the execution circuitry to perform operations corresponding to the atomic store to memory instruction, including to:
atomically store the 512-bit data to a memory location, bypassing the plurality of caches; and
store status information associated with the atomic store of the 512-bit data to the memory location in a register of the processor.

### Claim 36 (depends on 35)

The processor of claim 35, wherein the atomic store to memory instruction is an instruction to submit work to a device, and wherein the status information is indicative that the storage of the 512-bit data to the memory location has been stored in a work queue of the device.

### Claim 37 (depends on 35)

The processor of claim 35, wherein the status information is based on a received response related to the atomic store of the 512-bit data to the memory location.

### Claim 38 (depends on 35)

The processor of claim 35, wherein, to execute the decoded atomic store to memory instruction, the execution circuitry is to:
sequentially store different 64-bit portions of the 512-bit data from the eight sequential 64-bit registers to a storage location; and
concurrently store the 512-bit data from the storage location to the memory location.

### Claim 39 (depends on 35)

The processor of claim 35, wherein successful completion of the atomic store requires the memory location to be 64-byte aligned, wherein a memory type of the memory location is an uncacheable memory type, and wherein the execution circuitry is to atomically store the 512-bit data to the memory location via an uncacheable store operation.

### Claim 40

A system comprising:
a system memory; and
a processor coupled with the system memory, the processor comprising:
a plurality of caches;
fetch circuitry to fetch an atomic store to memory instruction;
decode circuitry coupled with the fetch circuitry, the decode circuitry to decode the atomic store to memory instruction, the atomic store to memory instruction having a field to specify a 64-bit register, wherein the 64-bit register is a first of eight sequential 64-bit registers, the eight sequential 64-bit registers to collectively store a 512-bit data; and
execution circuitry coupled with the decode circuitry, the execution circuitry to perform operations corresponding to the atomic store to memory instruction, including to:
atomically store the 512-bit data to a memory location, bypassing the plurality of caches; and
store status information associated with the atomic store of the 512-bit data to the memory location in a register of the processor.

### Claim 41 (depends on 40)

The system of claim 40, wherein the atomic store to memory instruction is an instruction to submit work to a device, and wherein the status information is indicative that the storage of the 512-bit data to the memory location has been stored in a work queue of the device.

### Claim 42 (depends on 40)

The system of claim 40, wherein successful completion of the atomic store requires the memory location to be 64-byte aligned, wherein a memory type of the memory location is an uncacheable memory type, and wherein the execution circuitry is to atomically store the 512-bit data to the memory location via an uncacheable store operation.