# US 12,007,929 B2 · Low-latency optical connection for CXL for a server CPU > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,007,929 B2 - Document ID: US12007929B2 - Status: Granted - Kind: B2 - Application number: 17/067,365 - Filed: 2020-10-09 - Published: 2022-04-14 - Granted: 2024-06-11 - Earliest claimed: 2020-10-09 - Assignees: Altera Corporation - Applicants: Intel Corporation - Inventors: Anshuman Thakur; Dheeraj Subbareddy; MD Altaf Hossain; Ankireddy Nalamalpu; Mahesh Kumashikar - Web page: https://patentgrep.com/patent/US12007929B2 ## CPC - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F 13/4068: {Electrical coupling} - G06F 13/4295: {using an embedded synchronisation} - G06F 2213/0026: PCI express - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path. ## Claims ### Claim 1 A processor having a system on a chip (SOC) architecture, comprising: one or more central processing units (CPUs) comprising multiple cores; an optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path that transmits and receives an optical bit stream directly after a link layer, bypassing multiple levels of the optical CXL protocol stack; and a CXL interface controller connected to the one or more CPUs to enable communication between the one or more CPUs and one or more CXL devices over the optical CXL communication path. ### Claim 2 (depends on 1) The processor of claim 1, wherein the CXL interface controller includes an optical interface to control the optical CXL communication path. ### Claim 3 (depends on 2) The processor of claim 2, wherein the optical interface comprises an optical transceiver to control communication between the one or more CPUs and the one or more CXL devices over the optical CXL communication path. ### Claim 4 (depends on 2) The processor of claim 2, further comprising an electrical communication path incorporating a logical electrical protocol stack having the multiple levels including a protocol layer, a transaction layer, the link layer, a MAC layer, a PHY layer, and a physical channel to transmit and receive an electrical bit stream to provide a dual CXL communication path. ### Claim 5 (depends on 4) The processor of claim 4, wherein the CXL interface controller further includes an electrical interface to control the electrical communication path. ### Claim 6 (depends on 5) The processor of claim 5, wherein the electrical interface and the electrical communication path comprise an Ethernet network interface based on Ethernet protocols. ### Claim 7 (depends on 5) The processor of claim 5, wherein the CXL interface controller multiplexes the dual CXL communication path between the electrical communication path and the optical CXL communication path through the electrical interface and the optical interface. ### Claim 8 (depends on 5) The processor of claim 5, wherein the CXL interface controller further includes a multiplexer to direct data frames to either the electrical communication path or the optical CXL communication path. ### Claim 9 (depends on 8) The processor of claim 8, wherein the multiplexer selects between the electrical interface and the optical interface using select lines. ### Claim 10 (depends on 8) The processor of claim 8, wherein the CXL interface controller controls selection by the multiplexer based on a physical distance between the one or more CXL devices and the one or more CPUs. ### Claim 11 A processor system on a chip (SOC), comprising: one or more central processing units (CPUs) comprising multiple cores; a dual Compute Express Link (CXL) communication path comprising: an electrical communication path incorporating a logical electrical CXL protocol stack having multiple levels including a protocol layer, a transaction layer, a link layer, a MAC layer, a PHY layer, and a physical channel to transmit and receive an electrical bit stream; and an optical CXL communication path incorporating a logical optical CXL protocol stack path that transmits and receives an optical bit stream directly after the link layer, bypassing several levels of the logical electrical CXL protocol stack; a multiplexer to direct data frames to either the electrical communication path or the optical CXL communication path; and at least one CXL device connected to the dual CXL communication path. ### Claim 12 (depends on 11) The processor SOC of claim 11, wherein a CXL interface controller includes an electrical interface to control the electrical communication path and an optical interface to control the optical CXL communication path. ### Claim 13 (depends on 12) The processor SOC of claim 12, wherein the CXL interface controller controls selection by the multiplexer based on a physical distance between the at least one CXL device and the one or more CPUs. ### Claim 14 (depends on 11) The processor SOC of claim 11, wherein the at least one CXL device comprises a memory device, a storage device, an accelerator device, a system management controller or a system boot device. ### Claim 15 (depends on 12) The processor SOC of claim 12, wherein the at least one CXL device comprises an on-chip component within the processor SOC. ### Claim 16 (depends on 12) The processor SOC of claim 12, wherein the at least one CXL device comprises an off-chip component. ### Claim 17 (depends on 12) The processor SOC of claim 12, wherein the at least one CXL device is located on a backside of a processor board of the processor SOC. ### Claim 18 (depends on 12) The processor SOC of claim 12, wherein the at least one CXL device is located on a separate I/O board located in a server rack. ### Claim 19 A method of fabricating a processor system on a chip (SOC), the method comprising: fabricating one or more central processing units (CPUs) comprising multiple cores; fabricating a dual Compute Express Link (CXL) communication path comprising: an electrical communication path incorporating a logical electrical CXL protocol stack having multiple levels including a protocol layer, a transaction layer, a link layer, a MAC layer, a PHY layer, and a physical channel to transmit and receive an electrical bit stream; and an optical CXL communication path incorporating a logical optical CXL protocol stack path that transmits and receives an optical bit stream directly after the link layer, bypassing several levels of the logical electrical CXL protocol stack; connecting a multiplexer to the optical CXL communication path to direct data frames to either select the electrical communication path or the optical CXL communication path. ### Claim 20 (depends on 19) The method of claim 19, further comprising a CXL interface controller with an electrical interface and an optical interface, each connected to the multiplexer. ### Claim 21 (depends on 20) The method of claim 20, further comprising configuring the electrical interface with an electrical physical layer to control communication between the one or more CPUs and one or more CXL devices over the electrical communication path. ### Claim 22 (depends on 20) The method of claim 20, further comprising configuring the optical interface with an optical transceiver to control communication between the one or more CPUs and one or more CXL devices over the optical CXL communication path.