# US 12,007,916 B2 · Local internal discovery and configuration of individually selected and jointly selected devices

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,007,916 B2
- Document ID: US12007916B2
- Status: Granted
- Kind: B2
- Application number: 18/295,143
- Filed: 2023-04-03
- Published: 2023-09-28
- Granted: 2024-06-11
- Earliest claimed: 2012-12-06
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: John Eric Linstadt
- Web page: https://patentgrep.com/patent/US12007916B2

## CPC

- G06F 13/1694: {Configuration of memory controller to different memory types}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0623: {for memory modules}
- G06F 12/0646: {Configuration or reconfiguration}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/1045: {Read-write mode select circuits}
- G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G06F 13/1678: {using bus width}
- G06F 2212/7206: Reconfiguration of flash memory system
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

## Claims

### Claim 1

A memory controller comprising:
a command interface for communicating commands with two or more memory devices including at least a first configurable width device;
a data interface for communicating data with the first configurable width device;
address assignment logic to obtain a device address for assigning to the first configurable width device, and to generate a device address setting command for setting the device address of the configurable width device, the device address setting command including a mask value transmitted over the command interface and a data pattern transmitted over the data interface, wherein the data pattern and the mask value are set such that a logic operation performed on the data pattern and the mask value maps to the device address; and
wherein subsequent to generating the device address setting command, the command interface communicates a memory operation command addressed to the first configurable width device using the device address, wherein the memory operation command causes the first configurable width device to perform a memory operation associated with the memory operation command.

### Claim 2 (depends on 1)

The memory controller of claim 1, wherein the device address setting command includes an address bit parameter to identify a bit of the device address, and wherein the mask value indicates which bit of the data pattern is assigned to the bit of the device address.

### Claim 3 (depends on 1)

The memory controller of claim 1, wherein the mask value comprises a single bit set to a first logic value and remaining bits set to a second logic value.

### Claim 4 (depends on 1)

The memory controller of claim 1, wherein the data pattern comprises a single bit set to a first logic value and remaining bits set to a second logic value.

### Claim 5 (depends on 1)

The memory controller of claim 1, wherein the logic operation comprises an OR reduction of a bitwise AND of the mask value and the data pattern.

### Claim 6 (depends on 1)

The memory controller of claim 1, wherein the memory operation command comprises a read command for reading data from memory cells of the configurable width device, and wherein the memory controller obtains the data from the data interface responsive to the read command.

### Claim 7 (depends on 1)

The memory controller of claim 1, wherein the memory operation command comprises a write command for writing data to memory cells of the configurable width device, and wherein the memory controller writes the data to the data interface in association with the write command.

### Claim 8

A method for operating a memory controller having a command interface shared between at least two memory devices, the method comprising:
obtaining, by address assignment logic, a device address for assigning to a first configurable width device of the at least two memory devices;
generating, by the address assignment logic, a device address setting command for setting the device address of the first configurable width device, the device address setting command including a mask value and a data pattern, wherein the data pattern and the mask value are set such that a logic operation performed on the data pattern and the mask value maps to the device address; and
transmitting the mask value to the configurable width device via the command interface and transmitting the data pattern to the first configurable width device via a data interface;
generating a memory operation command including the device address of the first configurable width device; and
sending the memory operation command on the command interface to cause the first configurable width device to perform a memory operation associated with the memory operation command.

### Claim 9 (depends on 8)

The method of claim 8, wherein the device address setting command includes an address bit parameter to identify a bit of the device address, and wherein the mask value indicates which bit of the data pattern is assigned to the bit of the device address.

### Claim 10 (depends on 8)

The method of claim 8, wherein the mask value comprises a single bit set to a first logic value and remaining bits set to a second logic value.

### Claim 11 (depends on 8)

The method of claim 8, wherein the data pattern comprises a single bit set to a first logic value and remaining bits set to a second logic value.

### Claim 12 (depends on 8)

The method of claim 8, wherein the logic operation comprises an OR reduction of a bitwise AND of the mask value and the data pattern.

### Claim 13

A memory controller coupled to at least two memory devices via a command interface, comprising:
device addressing means for obtaining a device address for assigning to a first configurable width device of the at least two memory devices;
device address setting command generating means for generating a device address setting command for setting the device address of the first configurable width device, the device address setting command including a mask value and a data pattern, wherein the data pattern and the mask value are set such that a logic operation performed on the data pattern and the mask value maps to the device address; and
device address setting command transmitting means for transmitting the mask value to the configurable width device via a command interface and transmitting the data pattern to the first configurable width device via a data interface memory command generating means for generating a memory operation command including the device address of the first configurable width device; and
memory operation command setting means for sending the memory operation command on the command interface to cause the first configurable width device to perform a memory operation associated with the memory operation command.

### Claim 14 (depends on 13)

The memory controller of claim 13, wherein the device address setting command includes an address bit parameter to identify a bit of the device address, and wherein the mask value indicates which bit of the data pattern is assigned to the bit of the device address.

### Claim 15 (depends on 13)

The memory controller of claim 13, wherein the mask value comprises a single bit set to a first logic value and remaining bits set to a second logic value.

### Claim 16 (depends on 13)

The memory controller of claim 13, wherein the data pattern comprises a single bit set to a first logic value and remaining bits set to a second logic value.

### Claim 17 (depends on 13)

The memory controller of claim 13, wherein the logic operation comprises an OR reduction of a bitwise AND of the mask value and the data pattern.