# US 12,007,915 B1 · Field programmable gate array-based low latency disaggregated system orchestrator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,007,915 B1 - Document ID: US12007915B1 - Status: Granted - Kind: B1 - Application number: 18/447,707 - Filed: 2023-08-10 - Granted: 2024-06-11 - Earliest claimed: 2023-08-10 - Assignees: Morgan Stanley Services Group Inc. - Applicants: Morgan Stanley Services Group Inc. - Inventors: Igor G. Muskatblit; Michael Gorbovitski; Joshua N. Elijah - Web page: https://patentgrep.com/patent/US12007915B1 ## CPC - G06F 13/1668: {Details of memory controller} - H04L 69/12: Protocol engines - G06F 2213/16: Memory access - G06F 2213/40: Bus coupling - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract An asynchronous computer-implemented disaggregated processing system including an ethernet transceiver configured to receive data, from a computing device over a data communications network. A core processor is configured to execute to process information associated with at least some of the received data and a memory is configured to store, via a memory controller, processed information from the core processor. A field programmable gate array is configured via an execution implementation directive to parse at least some of the received data; preprocess at least some of the parsed data for use by the core processor; route, to the core processor, the preprocessed data; receive, from the core processor, information associated with the preprocessed data; route, to the computing device, a response associated with the information associated with the preprocessed data received from the core processor; and store, via the memory controller, the information associated with the preprocessed data in the memory. ## Claims ### Claim 1 An asynchronous computer-implemented disaggregated processing system, comprising: an ethernet transceiver configured to receive data from at least one computing device over a data communications network; a first end node configured to process information associated with at least some of the received data; a memory configured to store, via a second end node, processed information from the first end node; and a field programmable gate array, configured to dynamically orchestrate a connection between the first end node and the second end node at least as a function of an execution implementation directive, wherein the field programmable gate array is configured to dynamically orchestrate the connection between the first end node and the second end node by: parsing, by the field programmable gate array, at least some of the received data; preprocessing, by the field programmable gate array, at least some of the parsed data for use by the first node; routing, by the field programmable gate array to the first node, the preprocessed data; receiving, by the field programmable gate array from the first node, information associated with the preprocessed data; and routing, by the field programmable gate array to the at least one computing device via the ethernet transceiver, a response associated with the information received from the first node. ### Claim 2 (depends on 1) The system of claim 1, further comprising a third end node, wherein the field programmable gate array is further configured to: preprocess at least some of the parsed data for use by the third end node, wherein at least one of the steps associated with parsing and preprocessing are in response to the information associated with the preprocessed data. ### Claim 3 (depends on 2) The system of claim 2, wherein the third end node is an artificial intelligence processing unit. ### Claim 4 (depends on 3) The system of claim 3, wherein field programmable gate array is further configured to: parse, preprocess, route, and store information simultaneously by executing steps in parallel. ### Claim 5 (depends on 1) The system of claim 1, wherein field programmable gate array is further configured to store, via the second end node, the information associated with the preprocessed data in the memory, and further wherein at least one of receiving and storing the information associated with the preprocessed data occurs via a compute express link. ### Claim 6 (depends on 1) The system of claim 1, wherein the parsing includes extracting and framing key data. ### Claim 7 (depends on 1) The system of claim 1, wherein the preprocessing includes filtering extraneous information from the parsed data. ### Claim 8 (depends on 1) The system of claim 1, wherein the field programmable gate array is further configured by each of a plurality of respective execution implementation directives to: parse, preprocess, route, receive, and store respective information simultaneously in parallel during various stages of execution of the respective execution implementation directives. ### Claim 9 (depends on 1) The system of claim 1, wherein the field programmable gate array is further configured to structure the response associated with the information associated with the preprocessed data received from the first end node prior to routing the response to the at least one computing device. ### Claim 10 (depends on 1) The system of claim 1, further comprising at least one of: a third end node; a second memory; a memory switch; an application-specific integrated circuit; and a memory expansion connector, wherein the field programmable gate array is further configured to interface with the at least one of the third end node, second memory, memory switch, application-specific integrated circuit, and a memory expansion connector, in parallel operations. ### Claim 11 (depends on 1) The system of claim 1, wherein the first end node is a domain specific application-specific integrated circuit (“ASIC”). ### Claim 12 (depends on 1) The system of claim 1, wherein first end node, the field programmable gate array, and the second end node are mounted on a shared printed circuit board. ### Claim 13 An asynchronous computer-implemented disaggregated processing method, comprising: dynamically orchestrating, by a field programmable gate array that is configured at least as a function of an execution implementation directive, a connection between a first end node and a second end node, by: parsing, by the field programmable gate array, at least some of data from at least one computing device and received by an ethernet transceiver over a data communications network; preprocessing, by the field programmable gate array, at least some of the parsed data for use by a first end node that is configured to process information associated with at least some of the received data; routing, by the field programmable gate array to the first end node, the preprocessed data; receiving, by the field programmable gate array from the first end node, information associated with the preprocessed data; and routing, by the field programmable gate array to the at least one computing device via the ethernet transceiver, a response associated with the information received from the first end node. ### Claim 14 (depends on 13) The method of claim 13, further comprising preprocess at least some of the parsed data for use by a third end node, wherein at least one of the steps associated with parsing and preprocessing are in response to the information associated with the preprocessed data. ### Claim 15 (depends on 14) The method of claim 14, wherein the third end node is an artificial intelligence processing unit. ### Claim 16 (depends on 15) The method of claim 15, further comprising: parsing, preprocessing, routing, and storing by the field programmable gate array, the information associated with the preprocessed data simultaneously by executing steps in parallel. ### Claim 17 (depends on 13) The method of claim 13, further comprising: storing, by the field programmable gate array via the second end node, the information associated with the preprocessed data in the memory, wherein at least one of receiving and storing the information associated with the preprocessed data occurs via a compute express link. ### Claim 18 (depends on 13) The method of claim 13, wherein the parsing includes extracting and framing key data. ### Claim 19 (depends on 13) The method of claim 13, wherein the preprocessing includes filtering extraneous information from the parsed data. ### Claim 20 (depends on 13) The method of claim 13, further comprising: parsing, preprocessing, routing, receiving, and storing, by the field programmable gate array, respective information simultaneously in parallel during various stages of execution of a plurality of respective execution implementation directives. ### Claim 21 (depends on 13) The method of claim 13, further comprising: structuring, by the field programmable gate array, the response associated with the information associated with the preprocessed data received from the first end node prior to routing the response to the at least one computing device. ### Claim 22 (depends on 13) The method of claim 13, further comprising: interfacing, by the field programmable gate array with at least one of a third end node, a second memory, a memory switch, an application-specific integrated circuit, and a memory expansion connector, in parallel operations. ### Claim 23 (depends on 13) The method of claim 13, wherein the first end node is a domain specific application-specific integrated circuit (“ASIC”). ### Claim 24 (depends on 13) The method of claim 13, further comprising mounting the first end node, the field programmable gate array, and the second end node on a shared printed circuit board.