On-chip interconnect for memory channel controllers
AssigneeGoogle Inc.
InventorsRahul Nagarajan, Hema Hariharan
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Abstract
Methods, systems, and apparatus, including computer-readable media, are described for an integrated circuit that accelerates machine-learning computations. The circuit includes processor cores that each include: multiple channel controllers; an interface controller for coupling each channel controller to any memory channel of a system memory; and a fetch unit in each channel controller. Each fetch is configured to: receive channel data that encodes addressing information; obtain, based on the addressing information, data from any memory channel of the system memory using the interface controller; and write the obtained data to a vector memory of the processor core via the corresponding channel controller that includes the respective fetch unit.
Claims20
An integrated circuit configured to accelerate machine-learning computations, the circuit comprising:
- a plurality of processor cores, each processor core comprising:
- a plurality of channel controllers;
- an interface controller configured to couple each of the plurality of channel controllers to each memory channel of a system memory;
- and
- a respective fetch unit in each of the plurality of channel controllers, the respective fetch unit being configured to:
- i) receive a request that encodes addressing information;
- ii) obtain, based on the addressing information, data from any memory channel of the system memory using the interface controller;
- and
- iii) write the data obtained from any memory channel to a vector memory of the processor core via the channel controller that includes the fetch unit.
A computer-implemented method performed using an integrated circuit configured to accelerate machine-learning computations, the integrated circuit comprising a system memory and a processor core that includes a plurality of channel controllers, the method comprising:
- receiving a plurality of requests, where each of the plurality of requests encodes addressing information;
- for a first request of the plurality of requests:
- identifying, based on addressing information of the first request, any memory location of any memory channel of the system memory;
- obtaining data from a memory location among any memory location of the system memory using an on-chip interconnect (OCI) interface that couples each of the plurality of channel controllers to each memory channel of the system memory;
- and
- writing, based on the addressing information of the first request, the data obtained from the memory location to a vector memory of the processor core.
Dependencies are inferred from the claim text.