# US 12,007,911 B2 · System and method for efficiently obtaining information stored in an address space > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,007,911 B2 - Document ID: US12007911B2 - Status: Granted - Kind: B2 - Application number: 17/874,962 - Filed: 2022-07-27 - Published: 2023-09-14 - Granted: 2024-06-11 - Earliest claimed: 2022-03-10 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Chun-Chu Chen-Jhy Archie Wu; Sumanth Jannyavula Venkata; Young deok Kim - Web page: https://patentgrep.com/patent/US12007911B2 ## CPC - G06F 3/0608: {Saving storage space on storage systems} - G06F 12/1408: {by using cryptography (for digital transmission H04L9/00)} - G06F 3/061: {Improving I/O performance} - G06F 3/0626: {Reducing size or complexity of storage systems} - G06F 3/064: {Management of blocks} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - H04L 9/3242: {involving keyed hash functions, e.g. message authentication codes [MACs], CBC-MAC or HMAC} - G06F 2212/1052: Security improvement - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A method of a memory device is provided. The method includes generating, by a controller of the memory device, a hashed index by hashing a source index comprising a namespace identification (NSID) and a keytag with a hash function; accessing, by the controller, a first storage address corresponding to the hashed index; comparing, by the controller, a tag portion corresponding to the first storage address with the source index to identify whether a conflict exists; and in response to identifying whether the conflict exists, obtaining, by the controller, information from the first storage address. ## Claims ### Claim 1 A method of a memory device, comprising: generating, by a controller of the memory device, a first hashed index by hashing a source index comprising a namespace identification (NSID) and a keytag with a first hash function; generating, by the controller, a second hashed index by hashing the source index comprising the NSID and the keytag with a second hash function; accessing, by the controller, a first storage address corresponding to the first hashed index or the second hashed index; comparing, by the controller, a tag portion corresponding to the first storage address with the source index to identify whether a conflict exists; and in response to identifying whether the conflict exists, obtaining, by the controller, information from the first storage address. ### Claim 2 (depends on 1) The method of claim 1, wherein the first storage address is comprised in a first memory, and wherein comparing, by the controller, the tag portion corresponding to the first storage address with the source index to identify whether the conflict exists further comprises: in response to identifying that the conflict exists, linking, by the controller, the first storage address in the first memory to an empty second storage address in the first memory. ### Claim 3 (depends on 1) The method of claim 1, wherein the first storage address is comprised in a first memory, wherein comparing, by the controller, the tag portion corresponding to the first storage address with the source index to identify whether the conflict exists further comprises: in response to identifying that the conflict exists, linking, by the controller, the first storage address in the first memory to an empty second storage address in a second memory. ### Claim 4 (depends on 1) The method of claim 1, wherein a redirection index pointing to the first storage address is comprised in a first type of memory that includes more entries than a second type of memory, and wherein the first hashed index or the second hashed index additionally includes portion of bits configured to point to the redirection index in the first type of memory that points to the first storage address in the second type of memory. ### Claim 5 (depends on 4) The method of claim 4, further comprising: determining, by the controller, a most frequently used (MFU) entry by counting, at least, the most recent entry accessed on the second type of memory; and adjusting, by the controller, an entry in the redirection index to point to the MFU entry on the second type of memory, and assigning a tail of line (TOL) of a first link list to point to a head of line (HOL) entry of a second link list. ### Claim 6 (depends on 1) The method of claim 1, further comprising: generating, by the controller, the first hashed index by hashing the source index using a first double hash function, comparing, by the controller, a tag portion corresponding to the first storage address with the source index to identify whether the conflict exists, and in response to identifying that the conflict exists, generating, by the controller, the second hashed index by hashing the source index using a second double hash function. ### Claim 7 (depends on 1) The method of claim 1, further comprising: concurrently generating, by the controller, the first hashed index by hashing the source index using a first double hash function and the second hashed index by hashing the source index using a second double hash function. ### Claim 8 (depends on 1) The method of claim 1, further comprising: determining, by the controller, whether to generate the first hashed index or the second hashed index according to a sequential double hash mode or a concurrent double hash mode based on a predetermined condition, wherein the predetermined condition is based on, at least one of, a prior throughput duration, a prior lookup dynamic random access memory (DRAM) transaction count as a dynamic selection, a static selection, or a progressive dynamic selection that is based on an accumulation of prior selection counts compared to a threshold. ### Claim 9 (depends on 1) The method of claim 1, wherein a head of line (HOL) link list index pointing to the first storage address is comprised in a static random access memory (SRAM) that includes at least 1.5× a number of entries than a number of entries in a dynamic random access memory (DRAM), and wherein the first hashed index or the second hashed index additionally includes a second predetermined number of bits in addition to a first predetermined number of bits and points to an entry in the HOL link list that points to the first storage address in DRAM. ### Claim 10 A system, comprising: a memory; and a controller configured to: generate a first hashed index by hashing a source index comprising a namespace identification (NSID) and a keytag with a first hash function; generate a second hashed index by hashing the source index comprising the NSID and the keytag with a second hash function; access A first storage address corresponding to the first hashed index or the second hashed index; compare a tag portion corresponding to the first storage address with the source index to identify whether a conflict exists; and in response to identifying whether the conflict exists, obtain information from the first storage address. ### Claim 11 (depends on 10) The system of claim 10, wherein the first storage address is comprised in a first memory, and wherein comparing the tag portion corresponding to the first storage address with the source index to identify whether the conflict exists further comprises: in response to identifying that the conflict exists, link, by the controller, the first storage address in the first memory to an empty second storage address in the first memory. ### Claim 12 (depends on 10) The system of claim 10, wherein the first storage address is comprised in a first memory, wherein comparing the tag portion corresponding to the first storage address with the source index to identify whether the conflict exists further comprises: in response to identifying that the conflict exists, link, by the controller, the first storage address in the first memory to an empty second storage address in a second memory. ### Claim 13 (depends on 10) The system of claim 10, wherein a redirection index pointing to the first storage address is comprised in a first type of memory that includes more entries than a second type of memory, and wherein the first hashed index or the second hashed index additionally includes a portion of bits configured to point to the redirection index in the first type of memory that points to the first storage address in the second type of memory. ### Claim 14 (depends on 13) The system of claim 13, wherein the controller is further configured to: determine a most frequently used (MFU) entry by counting, at least, the most recent entry accessed on the second type of memory; and adjust an entry in the redirection index to point to the MFU entry on the second type of memory, and assigning a tail of line (TOL) of a first link list to point to a head of line (HOL) entry of a second link list. ### Claim 15 (depends on 10) The system of claim 10, wherein the controller is further configured to: generate the first hashed index by hashing the source index using a first double hash function, compare a tag portion corresponding to the first storage address with the source index to identify whether the conflict exists, and in response to identifying that the conflict exists, generate the second hashed index by hashing the source index using a second double hash function. ### Claim 16 (depends on 10) The system of claim 10, wherein the controller is further configured to concurrently generate the first hashed index by hashing the source index using a first double hash function and the second hashed index by hashing the source index using a second double hash function. ### Claim 17 (depends on 10) The system of claim 10, wherein the controller is further configured to determine whether to generate the first hashed index or the second hashed index according to a sequential double hash mode or a concurrent double hash mode based on a predetermined condition, wherein the predetermined condition is based on, at least one of, a prior throughput duration, a prior lookup dynamic random access memory (DRAM) transaction count as a dynamic selection, a static selection, or a progressive dynamic selection that is based on an accumulation of prior selection counts compared to a threshold. ### Claim 18 (depends on 10) The system of claim 10, wherein a head of line (HOL) link list index pointing to the first storage address is comprised in a static random access memory (SRAM) that includes at least 1.5× a number of entries than a number of entries in a dynamic random access memory (DRAM), and wherein the first hashed index or the second hashed index additionally includes a second predetermined number of bits in addition to a first predetermined number of bits and points to the first storage address in DRAM. ### Claim 19 A storage device, comprising: a controller; and a storage medium, wherein the controller is configured to: generate a first hashed index by hashing a source index comprising a namespace identification (NSID) and a keytag with a first hash function; generate a second hashed index by hashing the source index comprising the NSID and the keytag with a second hash function; access a first storage address corresponding to the first hashed index or the second hashed index; compare a tag portion corresponding to the first storage address with the source index to identify whether a conflict exists; and in response to identifying whether the conflict exists, obtain the information from the first storage address. ### Claim 20 (depends on 19) The storage device of claim 19, wherein the first storage address is comprised in a first memory, and wherein comparing the tag portion corresponding to the first storage address with the source index to identify whether the conflict exists further comprises: in response to identifying that the conflict exists, linking, by the controller, the first storage address in the first memory to an empty second storage address in the first memory.