# US 12,007,907 B2 · Victim cache with write miss merging

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- Number: US 12,007,907 B2
- Document ID: US12007907B2
- Status: Granted
- Kind: B2
- Application number: 17/828,189
- Filed: 2022-05-31
- Published: 2022-09-15
- Granted: 2024-06-11
- Earliest claimed: 2019-05-24
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Naveen Bhoria; Timothy David Anderson; Pete Hippleheuser
- Web page: https://patentgrep.com/patent/US12007907B2

## CPC

- G06F 12/128: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
- G06F 9/3001: {Arithmetic instructions}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/546: {Message passing systems or structures, e.g. queues}
- G06F 11/1064: {in cache or content addressable memories}
- G06F 12/0215: {with look ahead addressing means}
- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)}
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 12/0806: Multiuser, multiprocessor or multiprocessing cache systems
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0815: Cache consistency protocols
- G06F 12/082: {Associative directories (G06F12/0822 takes precedence)}
- G06F 12/0853: Cache with multiport tag or data arrays
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing
- G06F 12/0884: Parallel mode, e.g. in parallel with main memory or CPU
- G06F 12/0888: using selective caching, e.g. bypass
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/0895: of parts of caches, e.g. directory or tag array
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 12/12: Replacement control
- G06F 12/121: using replacement algorithms
- G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning
- G06F 12/127: using additional replacement algorithms
- G06F 13/1605: {based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36)}
- G06F 13/1642: {with request queuing}
- G06F 13/1673: {using buffers}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 15/8069: {using a cache}
- G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/1015: {Read-write modes for single port memories, i.e. having either a random port or a serial port}
- G11C 7/106: {Data output latches}
- G11C 7/1075: {for multiport memories each having random access ports and serial ports, e.g. video RAM}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 7/1087: {Data input latches}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 29/72: {with optimized replacement algorithms}
- G11C 29/76: {using address translation or modifications}
- G06F 2212/1016: Performance improvement
- G06F 2212/1021: Hit rate improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/1041: Resource optimization
- G06F 2212/1044: Space efficiency improvement
- G06F 2212/301: In special purpose processing node, e.g. vector processor
- G06F 2212/454: Vector or matrix data
- G06F 2212/603: of operating mode, e.g. cache mode or local memory mode
- G06F 2212/6032: Way prediction in set-associative cache
- G06F 2212/6042: Allocation of cache space to multiple users or processors
- G06F 2212/608: Details relating to cache mapping
- G06F 2212/62: Details of cache specific to multiprocessor cache arrangements
- G11C 29/4401: {for self repair}
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.

## Claims

### Claim 1

A system comprising:
a processor;
a main cache;
a victim cache coupled to the main cache; and
a cache controller coupled to the processor, the main cache, and the victim cache and configured to:
receive, from the processor, a write command associated with a memory location and a set of data;
determine whether the write command is associated with a hit in the main cache or the victim cache; and
based on the write command not being associated with a hit in the main cache and the victim cache, store the set of data in the victim cache.

### Claim 2 (depends on 1)

The system of claim 1, wherein:
the write command is a first write command;
the set of data is a first set of data; and
the cache controller is further configured to:
receive a second write command associated with a second set of data;
determine whether the second write command is associated with the memory location of the first write command; and
based on the second write command being associated with the memory location of the first write command:
merge the first set of data and the second set of data to produce a merged set of data; and
store the merged set of data in the victim cache.

### Claim 3 (depends on 2)

The system of claim 2, wherein the cache controller is configured to merge the first set of data and the second set of data prior to the storing of the first set of data in the victim cache.

### Claim 4 (depends on 2)

The system of claim 2, wherein the cache controller is further configured to, based on the second write command being associated with the memory location of the first write command, merge at least one property of the first write command and the second write command from a group consisting of: a byte enable, a privilege level, and an indicator of a process run on the processor associated with the respective command.

### Claim 5 (depends on 2)

The system of claim 2, wherein the cache controller is further configured to, based on the second write command not being associated with the memory location of the first write command, store the first set of data and the second set of data in the victim cache in parallel.

### Claim 6 (depends on 1)

The system of claim 1, wherein the cache controller is further configured to:
receive a read command;
determine whether the read command is associated with the memory location of the write command; and
based on the read command being associated with the memory location of the write command:
evict the set of data from the victim cache; and
stall the read command until the set of data is evicted from the victim cache.

### Claim 7 (depends on 6)

The system of claim 6, wherein the cache controller is further configured to:
determine whether the read command is associated with a miss in the main cache; and
perform the evicting of the set of data from the victim cache and the stalling of the read command based on the read command being associated with a miss in the main cache.

### Claim 8 (depends on 1)

The system of claim 1, wherein the cache controller is further configured to:
receive a read command;
determine a cache address in the victim cache associated with the write command prior to completion of the determining of whether the write command is associated with a hit in the victim cache; and
store a set of evicted data evicted based on the read command in the victim cache at the cache address associated with the write command.

### Claim 9 (depends on 1)

The system of claim 1 wherein:
the victim cache includes a set of cache lines and a set of line bits; and
the storing of the set of data in the victim cache includes storing the set of data in a first cache line of the set of cache lines and setting a first line bit of the set of line bits to indicate that the first cache line is associated with a write-miss.

### Claim 10 (depends on 1)

The system of claim 1 wherein the main cache has an association type that is different from an association type of the victim cache.

### Claim 11 (depends on 10)

The system of claim 10, wherein the main cache is n-way associative and the victim cache is fully associative.

### Claim 12

A method comprising:
receiving a write command associated with a memory location and a set of data;
determining, based on the memory location, whether the write command is associated with a hit in a main cache or a victim cache; and
based on the write command not being associated with a hit in the main cache and the victim cache, storing the set of data in the victim cache.

### Claim 13 (depends on 12)

The method of claim 12, wherein:
the write command is a first write command;
the set of data is a first set of data; and
the method further comprises:
receiving a second write command associated with a second set of data;
determining whether the second write command is associated with the memory location of the first write command; and
determining, based on whether the second write command is associated with the memory location of the first write command, whether to merge the first set of data and the second set of data to produce a merged set of data and
store the merged set of data in the victim cache.

### Claim 14 (depends on 13)

The method of claim 13 further comprising, based on the second write command being associated with the memory location of the first write command, merging the first set of data and the second set of data prior to the storing of the first set of data in the victim cache.

### Claim 15 (depends on 13)

The method of claim 13 further comprising, based on the second write command being associated with the memory location of the first write command, merging at least one property of the first write command and the second write command from a group consisting of: a byte enable, a privilege level, and an indicator of a process associated with the respective command.

### Claim 16 (depends on 13)

The method of claim 13 further comprising, based on the second write command not being associated with the memory location of the first write command, storing the first set of data and the second set of data in the victim cache in parallel.

### Claim 17 (depends on 12)

The method of claim 12 further comprising:
receiving a read command;
determining whether the read command is associated with the memory location of the write command; and
determining, based on whether the read command is associated with the memory location of the write command, whether to evict the set of data from the victim cache and stall the read command until the set of data is evicted from the victim cache.

### Claim 18 (depends on 17)

The method of claim 17 further comprising:
determining whether the read command is associated with a miss in the main cache; and
determining, further based on whether the read command is associated with a miss in the main cache, whether to evict the set of data from the victim cache and stall the read command until the set of data is evicted from the victim cache.

### Claim 19 (depends on 12)

The method of claim 12 further comprising:
receiving a read command;
determining a cache address in the victim cache associated with the write command prior to completion of the determining of whether the write command is associated with a hit in the victim cache; and
storing a set of evicted data evicted based on the read command in the victim cache at the cache address associated with the write command.

### Claim 20 (depends on 12)

The method of claim 12 further comprising:
storing, in the victim cache, an indicator that the set of data is associated with a write-miss.