# US 12,007,901 B2 · Memory cache with partial cache line valid states > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,007,901 B2 - Document ID: US12007901B2 - Status: Granted - Kind: B2 - Application number: 18/171,617 - Filed: 2023-02-20 - Published: 2023-08-17 - Granted: 2024-06-11 - Earliest claimed: 2021-05-13 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Ilya Granovsky; Tom Greenshtein - Web page: https://patentgrep.com/patent/US12007901B2 ## CPC - G06F 12/0891: using clearing, invalidating or resetting means - G06F 12/0895: of parts of caches, e.g. directory or tag array - G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory} - G06F 12/0646: {Configuration or reconfiguration} - G06F 12/0846: Cache with multiple tag or data arrays being simultaneously accessible - G06F 12/0862: with prefetch - G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing - G06F 12/0888: using selective caching, e.g. bypass - G06F 12/0879: Burst mode - G06F 2212/1016: Performance improvement - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus includes a cache memory circuit configured to store a cache lines, and a cache controller circuit. The cache controller circuit is configured to receive a read request to an address associated with a portion of a cache line. In response to an indication that the portion of the cache line currently has at least a first sub-portion that is invalid and at least a second sub-portion that is modified relative to a version in a memory, the cache controller circuit is further configured to fetch values corresponding to the address from the memory, to generate an updated version of the portion of the cache line by using the fetched values to update the first sub-portion, but not the second sub-portion, of the portion of the cache line, and to generate a response to the read request that includes the updated version of the portion of the cache line. ## Claims ### Claim 1 An apparatus, comprising: a cache memory circuit configured to store a plurality of cache lines that include a plurality of entries; a cache controller circuit configured to: receive a write request to an address associated with a particular cache line, wherein the write request includes new values for a proper subset of entries in the particular cache line; and in response to a determination that a status of the particular cache line indicates that at least a first portion of the particular cache line is invalid and at least a second portion of the particular cache line is modified relative to memory locations at the associated address in a memory: retrieve a mask value that indicates valid and invalid entries of the particular cache line; store the new values in the proper subset of entries; send a request to a memory controller to store the new values in the proper subset of entries of the particular cache line to locations in the memory corresponding to the address; and update the mask value based on the store to the proper subset of entries. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the cache controller circuit is further configured to determine, using the updated mask value, whether any entry in the particular cache line remains invalid after the storing. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the cache controller circuit is further configured to: in response to a determination that one or more of the entries are invalid, store the updated mask value in place of at least one of the one or more entries. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein to store the updated mask value, the cache controller circuit is configured to: identify a particular invalid entry in the particular cache line, based on a significance of a position of the particular invalid entry within the particular cache line; shift a subset of valid entries based on a significance of positions of the subset of valid entries within the particular cache line; and store the updated mask value in a given entry vacated by the shifting. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the cache controller circuit is further configured to access the status of the particular cache line in a corresponding cache tag. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the cache controller circuit is further configured to update, using the updated mask value, the status of the particular cache line in the corresponding cache tag. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the cache controller circuit is further configured to: track validity of data stored in a given cache line for individual entries of the given cache line; and maintain respective cache tags for a plurality of portions of the given cache line. ### Claim 8 An apparatus, comprising: a cache memory circuit configured to store a plurality of cache lines that include a plurality of entries; a cache controller circuit configured to: receive a write request to an address associated with a particular cache line, wherein the write request includes new values for a proper subset of entries in the particular cache line; and in response to a determination that a status of the particular cache line indicates that at least a first portion of the particular cache line is invalid and at least a second portion of the particular cache line is modified relative to memory locations at the associated address in a memory: retrieve a mask value that indicates valid and invalid entries of the particular cache line; store the new values in the proper subset of entries; and update the mask value based on the store to the proper subset of entries; determine, using the updated mask value, whether any entry in the particular cache line remains invalid after the storing; and in response to a determination that none of the entries are invalid: update the status of the particular cache line to indicate all the entries of the particular cache line are valid; and discard the updated mask value. ### Claim 9 An apparatus, comprising: a cache memory circuit configured to store a plurality of cache lines that include a plurality of entries; a cache controller circuit configured to: receive a write request to an address associated with a particular cache line, wherein the write request includes new values for a proper subset of entries in the particular cache line; and in response to a determination that a status of the particular cache line indicates that at least a first portion of the particular cache line is invalid and at least a second portion of the particular cache line is modified relative to memory locations at the associated address in a memory: retrieve a mask value that indicates valid and invalid entries of the particular cache line; store the new values in the proper subset of entries; and update the mask value based on the store to the proper subset of entries; receive a notification that values for memory locations in the memory that correspond to one or more of the entries of the particular cache line have been modified outside of the cache memory circuit; and update the mask value based on the notification. ### Claim 10 A method comprising: setting, by a cache controller circuit coupled to a cache memory circuit, a value in a cache tag associated with a particular cache line to indicate a partial state, the partial state indicative of an invalid first portion and a modified second portion of the particular cache line; receiving, by the cache controller circuit, a partial write request for an address associated with the particular cache line, wherein the partial write request includes new values for a proper subset of entries in the particular cache line; storing, by the cache controller circuit, valid values of the partial write request in corresponding entries of the particular cache line without modifying remaining entries in the particular cache line; sending, by the cache controller circuit, a request to a memory circuit to store the new values in the proper subset of entries of the particular cache line to locations in the memory circuit corresponding to the address; in response to the cache tag indicating the partial state, accessing, by the cache controller circuit, a mask value that identifies entries of the invalid first portion; and updating, by the cache controller circuit, the mask value based on the storing. ### Claim 11 (depends on 10) The method of claim 10, further comprising: in response to determining, by the cache controller circuit using the updated mask value, that one or more of the entries of the particular cache line are invalid after the storing, writing the updated mask value in place of at least one of the invalid entries. ### Claim 12 A method comprising: setting, by a cache controller circuit coupled to a cache memory circuit, a value in a cache tag associated with a particular cache line to indicate a partial state, the partial state indicative of an invalid first portion and a modified second portion of the particular cache line; receiving, by the cache controller circuit, a partial write request for an address associated with the particular cache line, wherein the partial write request includes new values for a proper subset of entries in the particular cache line; storing, by the cache controller circuit, valid values of the partial write request in corresponding entries of the particular cache line without modifying remaining entries in the particular cache line; in response to the cache tag indicating the partial state, accessing, by the cache controller circuit, a mask value that identifies entries of the invalid first portion; update the mask value based on the store to the proper subset of entries; determining, by the cache controller circuit using the updated mask value, that all of the entries of the particular cache line are valid; updating, by the cache controller circuit, the value in the cache tag to indicate that all the entries are valid; and invalidating, by the cache controller circuit, the updated mask value. ### Claim 13 A method comprising: setting, by a cache controller circuit coupled to a cache memory circuit, a value in a cache tag associated with a particular cache line to indicate a partial state, the partial state indicative of an invalid first portion and a modified second portion of the particular cache line; receiving, by the cache controller circuit, a partial write request for an address associated with the particular cache line, wherein the partial write request includes new values for a proper subset of entries in the particular cache line; storing, by the cache controller circuit, valid values of the partial write request in corresponding entries of the particular cache line without modifying remaining entries in the particular cache line; in response to the cache tag indicating the partial state, accessing, by the cache controller circuit, a mask value that identifies entries of the invalid first portion; receiving, by the cache controller circuit, a notification that values for one or more memory locations in a memory corresponding to one or more of the entries of the particular cache line have been modified outside of the cache memory circuit; and updating the mask value based on the notification. ### Claim 14 (depends on 13) The method of claim 13, further comprising: in response to receiving the notification, determining, by the cache controller circuit, that a current state of the particular cache line indicates that all entries of the particular cache line valid; and in response to the determining, updating the state of the particular cache line to indicate that a particular portion of the entries is invalid. ### Claim 15 A system, comprising: a memory circuit; a processor circuit configured to generate read and write requests for addresses in the memory circuit; and a cache memory system configured to: indicate, for a particular cache line, a partial state indicating that the particular cache line currently includes a first portion of entries that is invalid and a second portion of entries that is modified relative to memory locations at a corresponding address in the memory circuit, wherein a mask value is used to indicate the first portion of entries; and in response to receiving a notification that values for one or more memory locations in the memory circuit corresponding to one or more of the entries of the particular cache line have been modified outside of the cache memory system, update the mask value based on the notification. ### Claim 16 (depends on 15) The system of claim 15, wherein the cache memory system is further configured to: track validity of data stored in individual bytes of the particular cache line; maintain a cache tag for the particular cache line; and store a status of a current state of the particular cache line in the cache tag. ### Claim 17 (depends on 16) The system of claim 16, wherein the cache memory system is further configured to: in response to a determination that one or more of the entries of the particular cache line are invalid after the storing, set the status in the cache tag to the partial state. ### Claim 18 (depends on 16) The system of claim 16, wherein the cache memory system is further configured to: in response to a determination that no entries of the particular cache line are invalid after the storing, set the status in the cache tag to a valid modified state that indicates that at least one entry is modified and no entries are invalid. ### Claim 19 (depends on 15) The system of claim 15, wherein the cache memory system is further configured to: in response to receiving a write request from the processor circuit for an address associated with the particular cache line, store new values for a proper subset of entries in the particular cache line; and update the mask value based on the storing. ### Claim 20 (depends on 15) The system of claim 15, wherein the cache memory system is further configured to: in response to receiving the notification, determine that an indicated state of the particular cache line indicates that all entries of the particular cache line are valid; and in response to the determination, update the state of the particular cache line to indicate that a particular portion of the entries is invalid.