# US 12,007,900 B2 · Data accessing method and data accessing system capable of providing high data accessing performance and low memory utilization > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,007,900 B2 - Document ID: US12007900B2 - Status: Granted - Kind: B2 - Application number: 17/984,211 - Filed: 2022-11-09 - Published: 2024-01-11 - Granted: 2024-06-11 - Earliest claimed: 2022-07-08 - Assignees: Realtek Semiconductor Corp. - Applicants: Realtek Semiconductor Corp. - Inventors: Chih-Hao Liu - Web page: https://patentgrep.com/patent/US12007900B2 ## CPC - G06F 12/02: Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) - G06F 12/0882: Page mode - G06F 12/0804: with main memory updating (G06F12/0806 takes precedence) - G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning - G06F 2212/1024: Latency reduction - G06F 2212/1044: Space efficiency improvement - G06F 2212/173: Vehicle or other transportation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A data accessing method includes providing a first memory including a plurality of memory pages, acquiring a usage order value of each memory page of the plurality of memory pages, acquiring a first usage order value having a highest priority from a plurality of usage order values corresponding to the plurality of memory pages in the first memory, updating the first memory after a first memory page having the first usage order value is used, acquiring a second usage order value having a highest priority from the updated first memory after the first memory is updated, and using a second memory page having the second usage order. ## Claims ### Claim 1 A data accessing method comprising: providing a first memory comprising a plurality of memory pages; acquiring a usage order value of each memory page of the plurality of memory pages in the first memory; acquiring a first usage order value having a highest priority from a plurality of usage order values each corresponding to each of the respective plurality of memory pages in the first memory; updating the first memory after a first memory page of the plurality of memory pages of the first memory having the first usage order value is used; acquiring a second usage order value having a highest priority from remaining memory pages of the plurality of memory pages of the first memory after the first memory is updated following usage of the first memory page; and using a second memory page of the first memory having the second usage order; wherein the plurality of memory pages are two-dimensional memory pages. ### Claim 2 (depends on 1) The method of claim 1, wherein acquiring the first usage order value having the highest priority from the plurality of usage order values each corresponding to each of the respective plurality of memory pages in the first memory comprises: acquiring a minimum row usage order value of usage order values in each row of the plurality of usage order values in the first memory; buffering the minimum row usage order value of the usage order values in each row to a second memory; and acquiring a minimum usage order value from the second memory as the first usage order value. ### Claim 3 (depends on 2) The method of claim 2, further comprising: updating a plurality of usage order values buffered in the second memory after the first memory is updated; and after the first memory page having the first usage order value is used, setting the first memory page to an unavailable state for updating the first memory. ### Claim 4 (depends on 1) The method of claim 1, wherein acquiring the second usage order value having the highest priority from the remaining memory pages of the plurality of memory pages of the first memory after the first memory is updated following usage of the first memory page comprises: acquiring a minimum row usage order value of usage order values in each row from the remaining memory pages of the plurality of memory pages having the plurality of usage order values in the first memory; buffering the minimum row usage order value of the usage order values in each row to a second memory; and acquiring a minimum usage order value from the second memory as the second usage order value. ### Claim 5 (depends on 4) The method of claim 4, further comprising after the second memory page having the second usage order value is used, setting the second memory page to an unavailable state for updating the second memory. ### Claim 6 (depends on 1) The method of claim 1, further comprising: converting the plurality of memory pages in the first memory to a plurality of consecutive memory pages or a plurality of discrete memory pages according to a mapping table. ### Claim 7 (depends on 1) The method of claim 1, wherein the plurality of memory pages in the first memory comprises at least one available memory page and at least one unavailable memory page, and the at least one unavailable memory page has no usage order value. ### Claim 8 (depends on 1) The method of claim 1, wherein the first memory is a static random access memory (SRAM), and the second memory is a register. ### Claim 9 (depends on 1) The method of claim 1, further comprising after the first memory is updated, when all memory pages in a certain row of the first memory are unavailable, labeling the certain row as a null row for reducing a scanning dimension. ### Claim 10 A data accessing system comprising: a first memory comprising a plurality of memory pages and configured to save data; a receiver configured to receive input data and write the input data to the first memory; a transmitter configured to read output data from the first memory; and a processor coupled to the first memory, the receiver, and the transmitter and configured to control the first memory, the receiver, and the transmitter; wherein the processor acquires a usage order value of each memory page of the plurality of memory pages in the first memory, the processor acquires a first usage order value having a highest priority from a plurality of usage order values each corresponding to each of the plurality of memory pages in the first memory, the transmitter and the receiver access data through accessing a first memory page of the plurality of memory pages of the first memory having the first usage order value, the processor updates the first memory after the first memory page of the plurality of memory pages of the first memory having the first usage order value is used, the processor acquires a second usage order value having a highest priority from remaining memory pages of the plurality of memory pages of the first memory following usage of the first memory page, the transmitter and the receiver access data through a second memory page of the first memory having the second usage order value, and the plurality of memory pages are two-dimensional memory pages. ### Claim 11 (depends on 10) The system of claim 10, wherein the processor acquires a minimum row usage order value of usage order values in each row of the plurality of usage order values in the first memory, a second memory is configured to buffer the minimum row usage order value of the usage order values in each row, and the processor acquires a minimum usage order value from the second memory as the first usage order value. ### Claim 12 (depends on 11) The system of claim 11, the processor updates a plurality of usage order values buffered in the second memory after the first memory is updated, and after the first memory page having the first usage order value is used, the first memory page is set to an unavailable state for updating the first memory. ### Claim 13 (depends on 10) The system of claim 10, wherein the processor acquires a minimum row usage order value of usage order values in each row from the remaining memory pages of the plurality of memory pages having the plurality of usage order values in the first memory, a second memory is configured to buffer the minimum row usage order value of the usage order values in each row, and the processor acquires a minimum usage order value from the second memory as the second usage order value. ### Claim 14 (depends on 13) The system of claim 13, wherein after the second memory page having the second usage order value is used, the second memory page is set to an unavailable state for updating the second memory. ### Claim 15 (depends on 10) The system of claim 10, wherein the processor converts the plurality of memory pages in the first memory to a plurality of consecutive memory pages or a plurality of discrete memory pages according to a mapping table. ### Claim 16 (depends on 10) The system of claim 10, wherein the plurality of memory pages in the first memory comprises at least one available memory page and at least one unavailable memory page, and the at least one unavailable memory page has no usage order value. ### Claim 17 (depends on 10) The system of claim 10, wherein the first memory is a static random access memory (SRAM), and the second memory is a register. ### Claim 18 (depends on 10) The system of claim 10, wherein after the first memory is updated, when all memory pages in a certain row of the first memory are unavailable, the certain row is labeled as a null row for reducing a scanning dimension.