# US 12,007,896 B2 · Apparatuses, systems, and methods for configuring combined private and shared cache levels in a processor-based system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,007,896 B2 - Document ID: US12007896B2 - Status: Granted - Kind: B2 - Application number: 17/834,682 - Filed: 2022-06-07 - Published: 2022-12-15 - Granted: 2024-06-11 - Earliest claimed: 2021-06-09 - Assignees: Ampere Computing LLC - Applicants: Ampere Computing LLC - Inventors: Richard James Shannon; Stephan Jean Jourdan; Matthew Robert Erler; Jared Eric Bendt - Web page: https://patentgrep.com/patent/US12007896B2 ## CPC - G06F 12/084: with a shared cache - G06F 12/0811: with multilevel cache hierarchies - G06F 12/0813: with a network or matrix configuration - G06F 12/0842: for multiprocessing or multitasking - G06F 12/0846: Cache with multiple tag or data arrays being simultaneously accessible - G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing - G06F 12/128: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel - G06F 2212/1024: Latency reduction - G06F 2212/152: Virtualized environment, e.g. logically partitioned system - G06F 2212/502: using adaptive policy - G06F 2212/60: Details of cache memory - G06F 2212/601: Reconfiguration of cache memory - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Apparatuses, systems, and methods for configuring combined private and shared cache levels in a processor-based system. The processor-based system includes a processor that includes a plurality of processing cores each including execution circuits which are coupled to respective cache(s) and a configurable combined private and shared cache, and which may receive instructions and data on which to perform operations from the cache(s) and the combined private and shared cache. A shared cache portion of each configurable combined private and shared cache can be treated as an independently-assignable portion of the overall shared cache, which is effectively the shared cache portions of all of the processing cores. Each independently-assignable portion of the overall shared cache can be associated with a particular client running on the processor as an example. This approach can provide greater granularity of cache partitioning of a shared cache between particular clients running on a processor. ## Claims ### Claim 1 A processor-based system, comprising: a first processing core including a configurable combined private and shared cache, the configurable combined private and shared cache configured to include a shared cache portion, the shared cache portion configured to be associated with a first client application; and a second processing core including a configurable combined private and shared cache, the configurable combined private and shared cache of the second processing core comprising a shared cache portion configured to be associated with the first client application. ### Claim 2 (depends on 1) The processor-based system of claim 1, wherein: the processor-based system further comprises an allocation bitmask corresponding to the first client application; and the allocation bitmask indicates that the shared cached portion is associated with the first client application. ### Claim 3 (depends on 1) The processor-based system of claim 1, wherein the shared cache portion is configured to be responsive to a replacement policy based on a capacity limit. ### Claim 4 (depends on 1) The processor-based system of claim 1, wherein the second processing core is configured to be disabled. ### Claim 5 (depends on 1) The processor-based system of claim 1, integrated into an integrated circuit (IC). ### Claim 6 (depends on 1) The processor-based system of claim 1, further integrated into a device selected from the group consisting of: a server, a computer, a portable computer, a desktop computer, a mobile computing device, a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter. ### Claim 7 A processor-based system comprising a means for processing including means for storing information, the means for storing information configured to include a configurable shared cache portion in a first processing core, the shared cache portion of the first processing core configured to be associated with a first client application, and a configurable shared cache portion in a second processor core, the shared cache portion of the second processing core configured to be associated with the first client application. ### Claim 8 A method of associating a shared cache portion of a cache, comprising: establishing a shared cache portion of a configurable combined private and shared cache in a first processing core; associating the shared cache portion of the configurable combined private and shared cache of the first processing core with a first client application; establishing a shared cache portion of a configurable combined private and shared cache in a second processing core; and associating the shared cache portion of the configurable combined private and shared cache of the second processing core with the first client application. ### Claim 9 (depends on 8) The method of claim 8, wherein associating the shared cache portion of the configurable combined private and shared cache of the first processing core with the first client application comprises setting a value of an allocation bitmask corresponding to the first client application to indicate that the shared cached portion is associated with the first client application. ### Claim 10 (depends on 9) The method of claim 9, further comprising selectively allocating an entry in the shared cache portion based on the allocation bitmask. ### Claim 11 (depends on 8) The method of claim 8, wherein the second processing core is disabled. ### Claim 12 (depends on 8) The method of claim 8, further comprising selectively allocating an entry in the shared cache portion based on a capacity limit. ### Claim 13 A non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a processor, cause the processor to: establish a shared cache portion of a configurable combined private and shared cache in a first processing core; associate the shared cache portion of the configurable combined private and shared cache of the first processing core with a first client application; establish a shared cache portion of a configurable combined private and shared cache in a second processing core; and associate the shared cache portion of the configurable combined private and shared cache of the second processing core with the first client application. ### Claim 14 (depends on 13) The non-transitory computer-readable medium of claim 13, having stored thereon computer-executable instructions which, when executed by a processor, cause the processor to associate the shared cache portion of the configurable combined private and shared cache of the first processing core with the first client application by causing the processor to set a value of an allocation bitmask corresponding to the first client application to indicate that the shared cached portion is associated with the first client application. ### Claim 15 (depends on 14) The non-transitory computer-readable medium of claim 14, having stored thereon computer-executable instructions which, when executed by a processor, further cause the processor to selectively allocate an entry in the shared cache portion based on the allocation bitmask. ### Claim 16 (depends on 13) The non-transitory computer-readable medium of claim 13, wherein the second processing core is disabled. ### Claim 17 (depends on 13) The non-transitory computer-readable medium of claim 13 having stored thereon computer-executable instructions which, when executed by a processor further cause the processor to: selectively allocate an entry in the shared cache portion based on a capacity limit.