# US 12,007,895 B2 · Scalable system on a chip

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- Number: US 12,007,895 B2
- Document ID: US12007895B2
- Status: Granted
- Kind: B2
- Application number: 17/821,305
- Filed: 2022-08-22
- Published: 2023-02-23
- Granted: 2024-06-11
- Earliest claimed: 2021-08-23
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Per H. Hammarlund; Eran Tamari; Lior Zimet; Sergio Kolor; Sergio V. Tota; Sagi Lahav; James Vash; Gaurav Garg; Jonathan M. Redshaw; Steven R. Hutsell; Harshavardhan Kaushikkar; Shawn M. Fukami
- Web page: https://patentgrep.com/patent/US12007895B2

## CPC

- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0813: with a network or matrix configuration
- G06F 12/0815: Cache consistency protocols
- G06F 12/0824: {Distributed directories, e.g. linked lists of caches}
- G06F 12/109: for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence)
- G06F 12/128: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
- G06F 13/161: {with latency improvement}
- G06F 13/1668: {Details of memory controller}
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 13/4068: {Electrical coupling}
- G06F 15/17368: {non hierarchical topologies}
- G06F 15/7807: {System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package}
- G06F 12/0833: {in combination with broadcast means (e.g. for invalidation or updating)}
- G06F 2212/1016: Performance improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/1048: Scalability
- G06F 2212/305: being part of a memory device, e.g. cache DRAM
- G06F 2212/455: Image or video data
- G06F 2212/657: Virtual address space management
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

## Claims

### Claim 1

A system, comprising:
a plurality of processor cores;
a plurality of graphics processing units;
a plurality of peripheral devices distinct from the processor cores and the graphics processing units;
one or more memory controller circuits configured to interface with a system memory; and
an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, the graphics processing units, and the peripheral devices;
wherein the interconnect fabric comprises at least two networks having heterogeneous operational characteristics; and
wherein the processor cores, the graphics processing units, the peripheral devices, the one or more memory controller circuits, and the interconnect fabric are included in a system on a chip (SOC) integrated onto one or more co-packaged semiconductor dies.

### Claim 2 (depends on 1)

The system of claim 1, wherein the interconnect fabric is configured to allow interconnection of a variable number of processor cores, graphics processing units, peripheral devices, or memory controller circuits.

### Claim 3 (depends on 1)

The system of claim 1, wherein the at least two networks include a coherent network interconnecting the processor cores and the one or more memory controller circuits.

### Claim 4 (depends on 1)

The system of claim 1, wherein the at least two networks include a relaxed-ordered network coupled to the graphics processing units and the one or more memory controller circuits.

### Claim 5 (depends on 4)

The system of claim 4, wherein the peripheral devices include a subset of devices, wherein the subset includes one or more of a machine learning accelerator circuit or a relaxed-order bulk media device, and wherein the relaxed-ordered network is further coupled to the subset of devices to the one or more memory controller circuits.

### Claim 6 (depends on 4)

The system of claim 4, wherein the at least two networks include an input-output network coupled to interconnect the peripheral devices and the one or more memory controller circuits.

### Claim 7 (depends on 6)

The system of claim 6, wherein the peripheral devices include one or more real-time devices.

### Claim 8 (depends on 1)

The system of claim 1, wherein the at least two networks comprise a first network that comprises one or more characteristics to reduce latency compared to a second network of the at least two networks.

### Claim 9 (depends on 8)

The system of claim 8, wherein the one or more characteristics comprise a shorter route than the second network.

### Claim 10 (depends on 8)

The system of claim 8, wherein the one or more characteristics comprise wiring in metal layers that have one or more lower latency characteristics than metal layers used for the wiring for the second network.

### Claim 11 (depends on 1)

The system of claim 1, wherein the at least two networks comprise a first network that comprises one or more characteristics to increase bandwidth compared to a second network of the at least two networks.

### Claim 12 (depends on 11)

The system of claim 11, wherein the one or more characteristics comprise an interconnect using a larger number of wires compared to an interconnect for the second network.

### Claim 13 (depends on 11)

The system of claim 11, wherein the one or more characteristics comprise wiring in metal layers that are denser than metal layers used for the wiring for the second network.

### Claim 14 (depends on 1)

The system of claim 1, wherein interconnect topologies employed by the at least two networks include at least one of a star topology, a mesh topology, a ring topology, a tree topology, a fat tree topology, a hypercube topology, or a combination of one or of the topologies.

### Claim 15 (depends on 1)

The system of claim 1, wherein the operational characteristics employed by the at least two networks include at least one of strongly-ordered memory coherence or relaxed-ordered memory coherence.

### Claim 16 (depends on 4)

The system of claim 4, wherein the at least two networks are physically and logically independent.

### Claim 17 (depends on 1)

The system of claim 1, wherein the at least two networks are physically separate in a first mode of operation, and wherein a first network of the at least two networks and a second network of the at least two networks are virtual and share a single physical network in a second mode of operation.

### Claim 18

A system on a chip (SOC), the SOC comprising:
a plurality of processor cores;
a plurality of graphics processing units;
a plurality of peripheral devices;
one or more memory controller circuits; and
an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices;
wherein the interconnect fabric comprises at least a first network and a second network, wherein the first network comprises one or more characteristics to reduce latency compared to the second network of the at least two networks, and wherein a given one of the one or more memory controller circuits is coupled to the first and second networks and configured to receive memory requests from both of the first and second networks; and
wherein the processor cores, the graphics processing units, the peripheral devices, the one or more memory controller circuits, and the interconnect fabric are integrated onto one or more co-packaged semiconductor dies.

### Claim 19 (depends on 18)

The SOC of claim 18, wherein the one or more characteristics comprise a shorter route for the first network over a surface of the semiconductor die than a route of the second network.

### Claim 20 (depends on 18)

The SOC of claim 18, wherein the one or more characteristics comprise wiring in metal layers have one or more lower latency characteristics than metal layers used for the wiring for the second network.

### Claim 21 (depends on 18)

The SOC of claim 18, wherein the second network comprises one or more second characteristics to increase bandwidth compared to the first network.

### Claim 22 (depends on 21)

The SOC of claim 21, wherein the one or more second characteristics comprise an interconnect having more wires compared to an interconnect in the second network.

### Claim 23 (depends on 21)

The SOC of claim 21, wherein the one or more second characteristics comprise wiring in metal layers that are denser than metal layers used for the wiring for the second network.

### Claim 24

A system on a chip (SOC), the SOC comprising:
a plurality of processor cores;
a plurality of graphics processing units;
a plurality of peripheral devices;
one or more memory controller circuits; and
an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices;
wherein the interconnect fabric comprises at least a first network and a second network, wherein the first network is physically and logically independent from the second network, and wherein the first and second networks have heterogeneous interconnect topologies; and
wherein the processor cores, the graphics processing units, the peripheral devices, the one or more memory controller circuits, and the interconnect fabric are integrated onto one or more co-packaged semiconductor dies.

### Claim 25 (depends on 24)

The SOC of claim 24, wherein the first network and the second network are physically separate in a first mode of operation, and wherein a first network of the at least two networks and a second network of the at least two networks are virtual and share a single physical network in a second mode of operation.