# US 12,007,890 B2 · Configurable in memory computing engine, platform, bit cells and layouts therefore

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- Number: US 12,007,890 B2
- Document ID: US12007890B2
- Status: Granted
- Kind: B2
- Application number: 18/139,785
- Filed: 2023-04-26
- Published: 2023-08-17
- Granted: 2024-06-11
- Earliest claimed: 2018-06-18
- Assignees: The Trustees of Princeton University
- Applicants: The Trustees of Princeton University
- Inventors: Naveen Verma; Hossein Valavi; Hongyang Jia
- Web page: https://patentgrep.com/patent/US12007890B2

## CPC

- G06F 12/0607: {Interleaved addressing}
- G06F 12/0207: {with multidimensional access, e.g. row/column, matrix}
- G06F 15/7821: {Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory}
- G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)}
- G06N 3/045: Combinations of networks
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G06N 3/0495: Quantised networks; Sparse networks; Compressed networks
- G06N 3/063: using electronic means
- G06N 3/065: Analogue means
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4094: Bit-line management or control circuits
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- G11C 11/412: using field-effect transistors only
- G11C 11/419: Read-write [R-W] circuits
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- G06F 2212/454: Vector or matrix data
- G11C 8/16: Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations.

## Claims

### Claim 1

An in-memory computing architecture, comprising:
a compute-in-memory (CIM) array of bit-cells configured to receive parallel bit-wise input signals via a first CIM array dimension and to receive one or more accumulation signals via a second CIM array dimension, wherein each plurality of bit-cells associated with a common analog accumulation signal forms a respective CIM channel configured to provide analog representation of a respective portion of a multi bit computation output signal; and
control circuitry configured to cause the CIM array to perform a multi-bit computing operation on the input and accumulation signals using single-bit internal circuits and signals;
wherein the multi-bit computing operation of the CIM array comprises bit-parallel/bit-serial (BPBS) computing, and
wherein said bit-parallel computing comprises:
loading different matrix-element bits into respective in-memory computing channels;
using respective barrel shifters, barrel shifting digitized outputs from the computing channels to implement thereby corresponding bit weightings; and
using respective accumulators, performing digital accumulation over all of the computing channels to yield a multi-bit matrix-element compute result; and
wherein said bit-serial computing comprises:
individually applying each bit of a vector element to the loaded matrix-element bits and storing each resulting digitized output; and
using respective barrel shifters, barrel shifting the stored digitized outputs associated with each vector element bit prior to a digital accumulation with stored digitized outputs corresponding to subsequent input vector bits.

### Claim 2 (depends on 1)

The in-memory computing architecture of claim 1, further comprising a reshaping buffer, configured to reshape a sequence of received data words to form the parallel bit-wise input signals.

### Claim 3 (depends on 1)

The in-memory computing architecture of claim 1, further comprising analog to digital converter (ADC) circuitry configured to process the plurality of CIM channel output signals to provide thereby a sequence of multi-bit output words.

### Claim 4 (depends on 3)

The in-memory computing architecture of claim 3, further comprising a near-memory computing path configured to provide said sequence of multi-bit output words as a computing result.

### Claim 5 (depends on 3)

The in-memory computing architecture of claim 3, wherein said ADC circuitry comprises, for each CIM channel, a respective ADC configured to digitize the CIM channel output signal, and a respective shift register configured to impart a respective binary weighting to the digitized CIM channel output signal to form thereby a respective portion of a multi-bit output word.

### Claim 6 (depends on 3)

The in-memory computing architecture of claim 3, wherein said ADC circuitry comprises, for each of a plurality of subsets of said CIM channels, a respective ADC configured to digitize a weighted analog summation of the CIM channel output signals of the respective subset of CIM channels to form thereby a respective portion of a multi-bit output word.

### Claim 7 (depends on 1)

The in-memory computing architecture of claim 1, further comprising a sparsity controller configured to mask zero-valued elements of the parallel bit-wise input signals such that said multi-bit computing operation avoids processing zero-valued elements of the parallel bit-wise input signals.

### Claim 8 (depends on 1)

The in-memory computing architecture of claim 1, wherein the input signals and accumulation signals are combined with existing signals within the CIM array.

### Claim 9 (depends on 1)

The in-memory computing architecture of claim 1, wherein the input signals and accumulation signals are separate from existing signals within the CIM array.

### Claim 10 (depends on 3)

The in-memory computing architecture of claim 3, wherein each ADC and respective accumulation signal forms an in-memory computing channel.

### Claim 11 (depends on 4)

The in-memory computing architecture of claim 4, wherein said near-memory computing path comprises one or more of digital barrel shifters, multiplexers, accumulators, look-up tables, and non-linear function elements.

### Claim 12 (depends on 4)

The in-memory computing architecture of claim 4, where the near-memory computing path is physically aligned with the in-memory-computing architecture to increase throughput therethrough.

### Claim 13 (depends on 1)

The in-memory computing architecture of claim 1, further comprising one or more configurable finite-state machines (FSMs) configured to control computational operation of the in-memory computing architecture.

### Claim 14 (depends on 13)

The in-memory computing architecture of claim 13, where the FSMs controlling the computational operation is configured to control parallel computing hardware utilized by some or all of a plurality of in-memory computing channels.

### Claim 15 (depends on 13)

The in-memory computing architecture of claim 13, wherein the FSMs control computations in accordance with software instructions loaded in a local memory.

### Claim 16 (depends on 2)

The in-memory computing architecture of claim 2, wherein the reshaping buffer is configured to convert external digital words of a first precision into a high-dimensionality input vector.

### Claim 17 (depends on 16)

The in-memory computing architecture of claim 16, wherein the reshaping buffer is configured to provide bits of the input vector elements in a sequenced and parallel manner to the CIM array.

### Claim 18 (depends on 2)

The in-memory computing architecture of claim 2, wherein the reshaping buffer is configured for alignment input data to ensure a desired utilization and throughput of in-memory-computing operations.

### Claim 19 (depends on 2)

The in-memory computing architecture of claim 2, wherein the reshaping buffer is configured to enable reuse and shifting of input data in accordance with convolutional-neural-network operations.

### Claim 20 (depends on 1)

The in-memory computing architecture of claim 1, wherein each bit-cell in said CIM array of bit-cells has a bit-cell circuit configuration comprising:
a bit-cell storage circuit coupled to at least one bit-cell compute device; and
a bit-cell capacitor coupled to the bit-cell compute device, the bit-cell capacitor being further coupled to one or more additional capacitors corresponding to other bit-cell capacitors without a switch between the bit-cell capacitors.

### Claim 21 (depends on 20)

The in-memory computing architecture of claim 20, wherein the bit-cell circuit configuration further comprises a cathode plate of the bit-cell capacitor being coupled to the bit-cell compute device.

### Claim 22 (depends on 20)

The in-memory computing architecture of claim 20, wherein the bit-cell circuit configuration further comprises an anode plate of the bit-cell capacitor being coupled to the additional capacitors.

### Claim 23 (depends on 20)

The in-memory computing architecture of claim 20, wherein the bit-cell circuit configuration further comprises the bit-cell compute device being configured to perform a compute operation with two operands.

### Claim 24 (depends on 20)

The in-memory computing architecture of claim 20, wherein the bit-cell circuit configuration enables implementation of XNOR or AND operations between data stored and data inputted.

### Claim 25 (depends on 20)

The in-memory computing architecture of claim 20, wherein a bit-cell circuit configuration comprising an interleaved layout for at least two bit-cells in which respective bit-cell capacitors are coupled together in at least two separate sets to enable thereby corresponding separate computations.

### Claim 26 (depends on 25)

The in-memory computing architecture of claim 25, wherein the sets of coupled bit-cell capacitors are laid out above one or more bit-cell transistors.

### Claim 27 (depends on 25)

The in-memory computing architecture of claim 25, wherein the bit-cells comprise charge-domain in-memory-computing bit-cells that drive one plate of a respective local capacitor, and wherein coupling to other bit-cell capacitors is achieved at another plate of the respective local capacitor.

### Claim 28 (depends on 27)

The in-memory computing architecture of claim 27, wherein the charge-domain in-memory-computing bit-cells are configured to implement XNOR or AND operations between stored data and inputted data.

### Claim 29 (depends on 25)

The in-memory computing architecture of claim 25, wherein an interleaved layout for charge-domain in-memory-computing bit-cells is provided such that bit-cell capacitors are coupled in multiple different sets configured to be selectively coupled via one or more peripheral switches.

### Claim 30 (depends on 25)

The in-memory computing architecture of claim 25, wherein an interleaved layout for charge-domain in-memory-computing bit-cells is provided such that bit-cell capacitors are coupled in multiple different sets so that there are X sets for X-way interleaving, wherein X in an integer greater than one.

### Claim 31 (depends on 26)

The in-memory computing architecture of claim 26, wherein a layout for charge-domain in-memory-computing bit-cells is provided such that different sets of coupled capacitors are laid out above the one or more bit-cell transistors.