# US 12,007,879 B2 · Automated test vector generation

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- Number: US 12,007,879 B2
- Document ID: US12007879B2
- Status: Granted
- Kind: B2
- Application number: 17/504,111
- Filed: 2021-10-18
- Published: 2022-04-21
- Granted: 2024-06-11
- Earliest claimed: 2020-10-20
- Assignees: Rosemount Aerospace Inc.
- Applicants: Rosemount Aerospace Inc.
- Inventors: Simone Fulvio Rollini; Rob C. North
- Web page: https://patentgrep.com/patent/US12007879B2

## CPC

- G06F 11/3608: {using formal methods, e.g. model checking, abstract interpretation (theorem proving G06N5/013)}
- G06F 11/3684: {for test design, e.g. generating new test cases}
- G06F 11/3447: {Performance evaluation by modeling}
- G06F 11/3688: {for test execution, e.g. scheduling of test suites}
- G06F 11/3692: {for test results analysis}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An algorithm and method for automatically generating test vectors for an LRU by deriving test vectors at the LRU boundary that, when simulated on the LRU, reproduce input and output of given test cases at the boundary of the individual requirements, and for knowing whether there are test cases that cannot be realised, i.e. test vectors cannot be derived at the LRU boundary to reproduce them at the boundary of individual requirements.

## Claims

### Claim 1

A method for testing software for an aerospace application, the method comprising:
translating an integrated model that includes individual requirement software models and hardware models, a test case sequence, and an initialization test vector sequence into a common formal language;
deriving a stability property for each individual requirement and incorporating the derived stability properties into the translated integrated model;
providing the translated initialization test vector sequence to the translated integrated model enriched with the derived stability properties to drive the translated integrated model to an initial state;
generating a sequence of test vectors from the initial state;
determining whether the test case sequence can be realized by simulating the sequence of test vectors on the translated integrated model to reproduce inputs and outputs of the test case sequence at a boundary of the each individual requirement;
producing at least one of a test vector table comprising verified test vectors if the test case sequence can be realized or an unrealizability report if the test case sequence cannot be realized; and
executing the verified test vectors on physical test equipment.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
producing an indication of an unknown status when time or memory elapses before a determination of whether the test case sequence can be realized is made.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
automatically generating and verifying the test vector sequence in a virtual environment before the test vector sequence is implemented on the physical test equipment.

### Claim 4

A testing method for an integrated model that includes individual requirement software models and hardware models, the method comprising:
translating the integrated model, a test case sequence and an initialization test vector sequence into a common formal language;
deriving a stability property for each individual requirement and incorporating the derived stability properties into the translated integrated model;
providing the translated initialization test vector sequence to the translated integrated model enriched with the derived stability properties to drive the translated integrated model to an initial state;
generating a sequence of test vectors from the initial state to realize the test case sequence;
determining whether the test case sequence can be realized by simulating the sequence of test vectors on the translated integrated model to reproduce inputs and outputs of the test case sequence at a boundary of the each individual requirement; and
providing an indication of whether the test case sequence can be realized.

### Claim 5 (depends on 4)

A non-transitory computer storage medium having instructions stored thereon which, when performed on a modelling system, perform the method of claim 4.

### Claim 6 (depends on 4)

The method of claim 4, further comprising producing a test vector table that includes verified test vectors if the test case sequence can be realized.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
executing the verified test vectors on physical test equipment.

### Claim 8 (depends on 4)

The method of claim 4, further comprising:
producing an unrealizability report if the test case sequence cannot be realized.

### Claim 9 (depends on 4)

The method of claim 4, further comprising:
producing an indication of an unknown status when time or memory elapses before a determination of whether the test case sequence can be realized is made.

### Claim 10 (depends on 4)

The method of claim 4, further comprising:
automatically generating and verifying the test vector sequence in a virtual environment before the test vector sequence is implemented on physical test equipment.