# US 12,007,860 B2 · Salvaging bad blocks in a memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,007,860 B2 - Document ID: US12007860B2 - Status: Granted - Kind: B2 - Application number: 18/075,958 - Filed: 2022-12-06 - Published: 2023-04-13 - Granted: 2024-06-11 - Earliest claimed: 2020-08-27 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Sri Rama Namala; Lu Tong; Kristopher Kopel; Sheng-Huang Lee; Chang H. Siau - Web page: https://patentgrep.com/patent/US12007860B2 ## CPC - G06F 11/2094: {Redundant storage or storage space (G06F11/2056 takes precedence)} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G06F 2201/85: Active fault masking without idle spares - G11C 16/26: Sensing or reading circuits; Data output circuits - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block). ## Claims ### Claim 1 A memory device comprising: a processor; a memory, storing instructions, which when executed, causes the processor to perform operations comprising: identifying that a first deck of a block of three-dimensional NAND has a defect of a type from an identified list of defect types; identifying that a second deck of the block does not have a defect from the identified list of defect types; testing the second deck to determine if it meets at least one quality criterion; responsive to determining that the second deck meets at least one quality criterion, marking the second deck as salvageable; receiving a memory device request; identifying a bias voltage for the first deck of the block; and servicing the memory device request serviced using NAND cells in the second deck, the servicing the memory device request comprising disabling the first deck during the servicing by applying the bias voltage to word lines of the first deck. ### Claim 2 (depends on 1) The memory device of claim 1, wherein one or more address bits in the memory device request indicate that the memory device request is indicating the second deck. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the operations of servicing the memory device request using NAND cells in the second deck is responsive to enablement of an option. ### Claim 4 (depends on 3) The memory device of claim 3, wherein the operations further comprise: determining that a number of defective blocks during operation of the memory device has exceeded a specified threshold and in response, enabling the option. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the identified list of defect types comprises a word line-to-word line short that only impacts data word lines; a resistive word line; a slow to program word line; and a word line that does not pass a raw bit error rate requirement. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the first deck is a bottom deck and the second deck is a top deck in the three-dimensional NAND. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the memory device request is a write command to write host data. ### Claim 8 A method of operating a memory device, the method comprising: identifying that a first deck of a block of three-dimensional NAND of the memory device has a defect of a type from an identified list of defect types; identifying that a second deck of the block does not have a defect from the identified list of defect types; testing the second deck to determine if it meets at least one quality criterion; responsive to determining that the second deck meets at least one quality criterion, marking the second deck as salvageable; receiving a memory device request; identifying a bias voltage for the first deck of the block; and servicing the memory device request serviced using NAND cells in the second deck, the servicing the memory device request comprising disabling the first deck during the servicing by applying the bias voltage to word lines of the first deck. ### Claim 9 (depends on 8) The method of claim 8, wherein one or more address bits in the memory device request indicate that the memory device request is indicating the second deck. ### Claim 10 (depends on 8) The method of claim 8, wherein servicing the memory device request using NAND cells in the second deck is responsive to enablement of an option. ### Claim 11 (depends on 10) The method of claim 10, wherein the method further comprises: determining that a number of defective blocks during operation of the memory device has exceeded a specified threshold and in response, enabling the option. ### Claim 12 (depends on 8) The method of claim 8, wherein the identified list of defect types comprises a word line-to-word line short that only impacts data word lines; a resistive word line; a slow to program word line; and a word line that does not pass a raw bit error rate requirement. ### Claim 13 (depends on 8) The method of claim 8, wherein the first deck is a bottom deck and the second deck is a top deck in the three-dimensional NAND. ### Claim 14 (depends on 8) The method of claim 8, wherein the memory device request is a write command to write host data. ### Claim 15 A non-transitory, machine-readable medium, storing instructions, which when executed, causes a hardware processor of a memory device to perform operations comprising: identifying that a first deck of a block of three-dimensional NAND has a defect of a type from an identified list of defect types; identifying that a second deck of the block does not have a defect from the identified list of defect types; testing the second deck to determine if it meets at least one quality criterion; responsive to determining that the second deck meets at least one quality criterion, marking the second deck as salvageable; receiving a memory device request; identifying a bias voltage for the first deck of the block; and servicing the memory device request serviced using NAND cells in the second deck, the servicing the memory device request comprising disabling the first deck during the servicing by applying the bias voltage to word lines of the first deck. ### Claim 16 (depends on 15) The non-transitory machine-readable medium of claim 15, wherein one or more address bits in the memory device request indicate that the memory device request is indicating the second deck. ### Claim 17 (depends on 15) The non-transitory machine-readable medium of claim 15, wherein the operations of servicing the memory device request using NAND cells in the second deck is responsive to enablement of an option. ### Claim 18 (depends on 17) The non-transitory machine-readable medium of claim 17, wherein the operations further comprise: determining that a number of defective blocks during operation of the memory device has exceeded a specified threshold and in response, enabling the option. ### Claim 19 (depends on 15) The non-transitory machine-readable medium of claim 15, wherein the identified list of defect types comprises a word line-to-word line short that only impacts data word lines; a resistive word line; a slow to program word line; and a word line that does not pass a raw bit error rate requirement. ### Claim 20 (depends on 15) The non-transitory machine-readable medium of claim 15, wherein the first deck is a bottom deck and the second deck is a top deck in the three-dimensional NAND.