# US 12,007,826 B2 · Unified retention and wake-up clamp apparatus and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,007,826 B2 - Document ID: US12007826B2 - Status: Granted - Kind: B2 - Application number: 17/128,076 - Filed: 2020-12-19 - Published: 2022-03-24 - Granted: 2024-06-11 - Earliest claimed: 2020-09-21 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Charles Augustine; Pascal Meinerzhagen; Suyoung Bang; Abdullah Afzal; Karthik Subramanian; Muhammad Khellah; Arvind Raman - Web page: https://patentgrep.com/patent/US12007826B2 ## CPC - G06F 1/324: by lowering clock frequency - G06F 1/08: Clock generators with changeable or programmable clock frequency - G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators} - G06F 1/3296: by lowering the supply or operating voltage - H03K 19/017509: {Interface arrangements} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Described is a controller that provides in-situ state retention using a closed loop global retention clamp. The controller addresses di/dt and reliability constraints using an adaptive scheme where steps with smaller current are quickly changed whereas steps with larger current are changed slowly. The loop controller of a voltage regulator is modified for controlling not only retention Vmin during a low power state (e.g., C1LP), but also to control fast wake up the low power state (e.g., from C1LP and from C6). ## Claims ### Claim 1 An apparatus comprising: a plurality of power gates coupled to an input power supply rail and an output power supply rail; a shifter to generate a control word to control the plurality of power gates; and a controller to instruct the shifter when to shift up a value of the control word, shift down the value of the control word, or maintain the value of the control word, wherein the controller is to shift up or shift in non-monotonic manner to reduce error between a reference beat frequency and a beat frequency of a free-running oscillator. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the controller is to operate in retention mode or wakeup mode. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein, in the retention mode, the controller is to instruct the shifter to shift up the value of the control word when a voltage on the output power supply rail is less than a retention voltage and when the voltage on the output power supply rail has a negative slope or substantially zero slope. ### Claim 4 (depends on 2) The apparatus of claim 2, wherein, in the retention mode, the controller is to instruct the shifter to shift down the value of the control word when a voltage on the output power supply rail is greater than a retention voltage and when the voltage on the output power supply rail has a positive slope or when the voltage on the output power supply rail has a substantially zero slope. ### Claim 5 (depends on 2) The apparatus of claim 2, wherein, in the wakeup mode, the controller is to instruct the shifter to shift up the value of the control word if a slope of a voltage on the output power supply rail is less than or equal than a reference slope. ### Claim 6 (depends on 2) The apparatus of claim 2, wherein, in the wakeup mode, the controller is to instruct the shifter to maintain the value of the control word if a slope of a voltage on the output power supply rail is greater than a reference slope. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the free-running oscillator is to generate a first clock, wherein the apparatus comprises a clock synchronizer to synchronize the first clock with a second clock. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the controller comprises a counter, wherein the clock synchronizer is to generate a third clock, and wherein the counter is to determine the frequency of the first clock via the third clock. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the counter is to receive the second clock. ### Claim 10 (depends on 8) The apparatus of claim 8, wherein the controller comprises a first comparator to compare an output of the counter with a digital value indicating a past frequency count of the first clock, and wherein the first comparator is to generate an output indicative of a direction in change in frequency of the first clock relative the past frequency count. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the controller comprises a second comparator to compare the output of the counter with a reference frequency count, wherein the second comparator is to generate an output indicating an error between the first clock relative to the reference frequency count. ### Claim 12 (depends on 11) The apparatus of claim 11 comprises a logic to generate the control word according to the outputs of the first and second comparators. ### Claim 13 (depends on 1) The apparatus of claim 1, wherein the plurality of power gates comprises p-type devices. ### Claim 14 A system comprising: a memory; a processor coupled to the memory; and a wireless interface communicatively coupled to the processor, wherein the processor includes a low dropout regulator comprising: a plurality of power gates coupled to an input power supply rail and an output power supply rail; a shifter to generate a control word to control the plurality of power gates; and a controller to instruct the shifter when to shift up a value of the control word, shift down the value of the control word, or maintain the value of the control word, wherein the controller is to shift up or shift in non-monotonic manner to reduce error between a reference beat frequency and a beat frequency of a free-running oscillator. ### Claim 15 (depends on 14) The system of claim 14, wherein the controller is to operate in retention mode or wakeup mode. ### Claim 16 (depends on 15) The system of claim 15, wherein, in the retention mode, the controller is to instruct the shifter to shift up the value of the control word when a voltage on the output power supply rail is less than a retention voltage and when the voltage on the output power supply rail has a negative slope or substantially zero slope. ### Claim 17 (depends on 15) The system of claim 15, wherein, in the retention mode, the controller is to instruct the shifter to shift down the value of the control word when a voltage on the output power supply rail is greater than a retention voltage and when the voltage on the output power supply rail has a positive slope or when the voltage on the output power supply rail has a substantially zero slope. ### Claim 18 (depends on 15) The system of claim 15, wherein, in the wakeup mode, the controller is to instruct the shifter to shift up the value of the control word if a slope of a voltage on the output power supply rail is less than or equal than a reference slope. ### Claim 19 (depends on 15) The system of claim 15, wherein, in the wakeup mode, the controller is to instruct the shifter to maintain the value of the control word if a slope of a voltage on the output power supply rail is greater than a reference slope.