# US 12,007,823 B2 · Power management of a processor and a platform in active state and low power state

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- Number: US 12,007,823 B2
- Document ID: US12007823B2
- Status: Granted
- Kind: B2
- Application number: 17/702,504
- Filed: 2022-03-23
- Published: 2022-12-08
- Granted: 2024-06-11
- Earliest claimed: 2021-06-04
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Pannerkumar Rajagopal; Raghavendra N; Ovais Pir; Prakash Pillai; Sagar C. Pawar
- Web page: https://patentgrep.com/patent/US12007823B2

## CPC

- G06F 1/1677: {for detecting open or closed state or particular intermediate positions assumed by movable parts of the enclosure, e.g. detection of display lid position with respect to main body in a laptop, detection of opening of the cover of battery compartment}
- G06F 1/3231: Monitoring the presence, absence or movement of users
- G06F 1/3215: Monitoring of peripheral devices
- G06F 1/3265: {Power saving in display device}
- G06F 1/3287: by switching off individual functional units in the computer system
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., S0 state) and would otherwise draw power in the S0 state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC.

## Claims

### Claim 1

An apparatus, comprising:
an interconnect fabric;
a plurality of processor cores, wherein the plurality of processor cores are coupled to one another via the interconnect fabric;
a first wake circuitry configured to wake up a first circuitry, wherein the first wake circuitry is configured to implement a first category of wake mechanisms;
a second wake circuitry configured to wake up a second circuitry, wherein the second wake circuitry is configured to implement a second category of wake mechanisms; and
a control circuitry coupled to the first wake circuitry and the second wake circuitry, wherein the control circuitry is configured to turn off the first wake circuitry and the second wake circuitry when a processor core of the plurality of processor cores is in an active operational mode.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising a biological sensor coupled to the control circuitry, wherein:
the biological sensor is capable of detecting human activity; and
when the processor core enters a low power operational mode, the control circuitry is to turn on the biological sensor and the second wake circuitry but not the first wake circuitry.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the control circuitry is to turn on the first wake circuitry when the biological sensor detects user activity in the low power operational mode.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the low power operational mode is an S0ix state as defined by Advanced Configuration and Power Interface (ACPI) specification, or wherein the low power operational mode is a connected standby state and the active operational mode is an S0 state as defined by the ACPI specification.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein an operating system, which is to execute on one or more processor cores of the plurality of processor cores, is to issue an interrupt to the control circuitry to turn on the first wake circuitry and the second wake circuitry.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the control circuitry is to send a control message to each of the first wake circuitry and the second wake circuitry to turn on or off each of the first wake circuitry and the second wake circuitry, and to receive an acknowledgment message from each of the first wake circuitry and the second wake circuitry to confirm successful reception of the control message by each of the first wake circuitry and the second wake circuitry.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein to be turned on by the control circuitry, the first wake circuitry requires a user presence and the second wake circuitry does not require a user presence.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the first wake circuitry is responsive to at least one of a power button press, a keyboard press, or a touchpad activation.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the second wake circuitry is to detect a magic packet.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the second wake circuitry comprises a wake on voice wake mechanism.

### Claim 11

An apparatus, comprising:
a plurality of wake circuitries including first and second wake circuitry configured to implement first and second categories of wake mechanisms, respectively;
a plurality of circuits including first and second circuits coupled to a processor, wherein the first and second wake circuitry are configured to wake up the first and second circuits, respectively; and
a control circuitry coupled to the plurality of wake circuitries, wherein the control circuitry is capable of sending control messages to the plurality of wake circuitries to turn off the first and second wake circuitry when the processor is in an active operational mode.

### Claim 12 (depends on 11)

The apparatus of claim 11, further comprising a sensor hub coupled to the control circuitry, wherein the sensor hub is to provide an indication to the control circuitry about one or more sensors.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the control circuitry is to selectively turn on one or more of wake circuitries of the plurality of wake circuitries, based on a user presence detected by the sensor hub, when the apparatus is in a low power operational mode.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the low power operational mode is an S0ix state as defined by Advanced Configuration and Power Interface (ACPI) specification, or wherein the low power operational mode is a connected standby state.

### Claim 15 (depends on 11)

The apparatus of claim 11, wherein the first circuit comprises at least one of a Peripheral Component Interface Express controller, a Universal Serial Bus controller, an Ethernet controller and an Audio controller.

### Claim 16

A system, comprising:
a processor;
a sensor;
a first wake circuitry;
a second wake circuitry; and
a control circuitry coupled to the processor, the sensor and the first and second wake circuitries, wherein the control circuitry is to:
turn off the first and second wake circuitries when the processor is in an active operational mode; and
when the processor is in a low power operational mode, turn on the first wake circuitry if the sensor detects a user presence, turn off the first wake circuitry if the sensor does not detect the user presence, and turn on the second wake circuitry regardless of whether the sensor detects the user presence, wherein the sensor is to continuously poll for the user presence to cause the control circuitry to selectively turn on the first wake circuitry while the second wake circuitry is turned on.

### Claim 17 (depends on 16)

The system of claim 16, wherein the control circuitry is to turn on the sensor when the processor enters the low power operational mode.

### Claim 18 (depends on 16)

The system of claim 16, wherein the second wake circuitry is to detect a magic packet.

### Claim 19 (depends on 16)

The system of claim 16, wherein the second wake circuitry comprises a wake on voice wake mechanism.