# US 12,007,437 B2 · Test method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,007,437 B2 - Document ID: US12007437B2 - Status: Granted - Kind: B2 - Application number: 17/864,342 - Filed: 2022-07-13 - Published: 2023-03-02 - Granted: 2024-06-11 - Earliest claimed: 2021-09-01 - Assignees: Fuji Electric Co., Ltd. - Applicants: Fuji Electric Co., Ltd. - Inventors: Kenichi Ishii; Atsushi Yoshida; Tomonori Mori; Takashi Shiigi - Web page: https://patentgrep.com/patent/US12007437B2 ## CPC - G01R 31/275: {for testing individual semiconductor components within integrated circuits} - G01R 31/2894: {Aspects of quality control [QC] (G01R31/31718 takes precedence; program control for QC G05B19/41875)} - G01R 31/2608: {for testing bipolar transistors} - G01R 31/2617: {for measuring switching properties thereof} - G01R 31/2856: {Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]} - G01R 31/2837: {Characterising or performance testing, e.g. of frequency response (transient response G01R27/28)} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract Provided is a test method of a semiconductor device under test, the test method comprising: controlling the semiconductor device under test to an on state by inputting a control signal to the semiconductor device under test; and observing the semiconductor device under test at a time of controlling the semiconductor device under test in the on state to an off state and evaluating the semiconductor device under test, wherein the semiconductor device under test includes one semiconductor device under test or a plurality of semiconductor devices under test, and in the controlling to the on state, a length of an on-time for which the one semiconductor device under test or the plurality of semiconductor devices under test are set to the on state is adjusted based on a magnitude of a variation in a delay time of the control signal. ## Claims ### Claim 1 A test method of a semiconductor device under test, the test method comprising: controlling the semiconductor device under test to an on state by inputting a control signal to the semiconductor device under test; and observing the semiconductor device under test at a time of controlling the semiconductor device under test in the on state to an off state and evaluating the semiconductor device under test, wherein the semiconductor device under test includes one semiconductor device under test or a plurality of semiconductor devices under test, and in the controlling to the on state, a length of an on-time for which the one semiconductor device under test or the plurality of semiconductor devices under test are set to the on state is adjusted based on a magnitude of a variation in a delay time of the control signal among a plurality of regions in one of the one or the plurality of semiconductor devices under test or among the plurality of semiconductor devices under test. ### Claim 2 (depends on 1) The test method according to claim 1, wherein in the controlling to the on state, a time of the on state is adjusted based on a maximum value of the delay time of the control signal. ### Claim 3 (depends on 1) The test method according to claim 1, wherein the larger of the variation in the delay time is, the longer of the on-time is set. ### Claim 4 (depends on 1) The test method according to claim 1, adjusting an inductive component connected in series with the semiconductor device under test, according to a time after the semiconductor device under test is controlled to the on state until a variation in a current flowing through the plurality of regions or a current flowing through the plurality of semiconductor devices under test becomes equal to or smaller than a constant value. ### Claim 5 (depends on 4) The test method according to claim 4, adjusting the inductive component so that the current flowing through the semiconductor device under test reaches a predetermined value of a test current, after a timing until the variation in the current becomes equal to or smaller than the constant value. ### Claim 6 (depends on 1) The test method according to claim 1, further comprising acquiring a defect rate of a module when the semiconductor device under test in a chip state determined as being non-defective in the evaluating is incorporated into the module, wherein in the controlling to the on state, the on-time is adjusted based on the defect rate of the module. ### Claim 7 (depends on 1) The test method according to claim 1, wherein in the controlling to the on state, the on-time is set to at least 100 μs. ### Claim 8 (depends on 1) The test method according to claim 1, wherein in the controlling to the on state, the on-time is set so that a variation in an in-plane current of the semiconductor device under test at a time when the on-time elapses becomes 20% or less. ### Claim 9 (depends on 1) The test method according to claim 1, performing the controlling to the on state by varying the on-time for a plurality of reference semiconductor devices having defects formed in advance, detecting the on-time for which a defect rate in the evaluating for the plurality of reference semiconductor devices becomes equal to or larger than a reference value, and adjusting the on-time in the controlling to the on state for the semiconductor device under test, based on the detected on-time. ### Claim 10 (depends on 2) The test method according to claim 2, wherein the larger of the variation in the delay time is, the longer of the on-time is set. ### Claim 11 (depends on 2) The test method according to claim 2, adjusting an inductive component connected in series with the semiconductor device under test, according to a time after the semiconductor device under test is controlled to the on state until a variation in a current flowing through the plurality of regions or a current flowing through the plurality of semiconductor devices under test becomes equal to or smaller than a constant value. ### Claim 12 (depends on 3) The test method according to claim 3, adjusting an inductive component connected in series with the semiconductor device under test, according to a time after the semiconductor device under test is controlled to the on state until a variation in a current flowing through the plurality of regions or a current flowing through the plurality of semiconductor devices under test becomes equal to or smaller than a constant value. ### Claim 13 (depends on 2) The test method according to claim 2, further comprising acquiring a defect rate of a module when the semiconductor device under test in a chip state determined as being non-defective in the evaluating is incorporated into the module, wherein in the controlling to the on state, the on-time is adjusted based on the defect rate of the module. ### Claim 14 (depends on 3) The test method according to claim 3, further comprising acquiring a defect rate of a module when the semiconductor device under test in a chip state determined as being non-defective in the evaluating is incorporated into the module, wherein in the controlling to the on state, the on-time is adjusted based on the defect rate of the module. ### Claim 15 (depends on 4) The test method according to claim 4, further comprising acquiring a defect rate of a module when the semiconductor device under test in a chip state determined as being non-defective in the evaluating is incorporated into the module, wherein in the controlling to the on state, the on-time is adjusted based on the defect rate of the module. ### Claim 16 (depends on 5) The test method according to claim 5, further comprising acquiring a defect rate of a module when the semiconductor device under test in a chip state determined as being non-defective in the evaluating is incorporated into the module, wherein in the controlling to the on state, the on-time is adjusted based on the defect rate of the module. ### Claim 17 (depends on 2) The test method according to claim 2, wherein in the controlling to the on state, the on-time is set to at least 100 μs. ### Claim 18 (depends on 3) The test method according to claim 3, wherein in the controlling to the on state, the on-time is set to at least 100 μs. ### Claim 19 (depends on 4) The test method according to claim 4, wherein in the controlling to the on state, the on-time is set to at least 100 μs. ### Claim 20 (depends on 5) The test method according to claim 5, wherein in the controlling to the on state, the on-time is set to at least 100 μs. ### Claim 21 (depends on 1) The test method according to claim 1, further comprising: evaluating the magnitude of the variation in the delay time of the control signal.