# US 12,007,436 B2 · Test circuit and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,007,436 B2 - Document ID: US12007436B2 - Status: Granted - Kind: B2 - Application number: 18/363,143 - Filed: 2023-08-01 - Published: 2023-11-23 - Granted: 2024-06-11 - Earliest claimed: 2019-12-13 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Hsieh-Hung Hsieh; Yen-Jen Chen; Tzu-Jin Yeh - Web page: https://patentgrep.com/patent/US12007436B2 ## CPC - G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)} - G01R 31/3004: {Current or voltage test} - G01R 27/28: Measuring attenuation, gain, phase shift or derived characteristics of electric four pole networks, i.e. two-port networks; Measuring transient response (in line transmission systems H04B3/46) - G01R 31/2853: {Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66)} - G01R 31/2879: {related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract An IC includes a device-under-test (DUT) configured to receive a first AC signal at a first node and output a second AC signal at a second node, the second AC signal being based on the first AC signal, and first and second detection circuits. Each of the first and second detection circuits includes a first gain stage coupled to a corresponding one of the first or second nodes through a first capacitive device, a second gain stage in a cascade arrangement with the first gain stage, and a low-pass filter configured to generate a DC signal based on an output signal of the second gain stage. ## Claims ### Claim 1 An integrated circuit (IC) comprising: a device-under-test (DUT) configured to receive a first alternating current (AC) signal at a first node and output a second AC signal at a second node, the second AC signal being based on the first AC signal; and first and second detection circuits, wherein each of the first and second detection circuits comprises: a first gain stage coupled to a corresponding one of the first or second nodes through a first capacitive device; a second gain stage in a cascade arrangement with the first gain stage; and a low-pass filter configured to generate a direct current (DC) signal based on an output signal of the second gain stage. ### Claim 2 (depends on 1) The IC of claim 1, further comprising: a ring oscillator configured to generate an oscillation signal; and a low-pass filter coupled between the ring oscillator and the first node and configured to output the AC signal based on the oscillation signal. ### Claim 3 (depends on 2) The IC of claim 2, wherein the ring oscillator is configured to generate the oscillation signal having a frequency ranging from 1 gigahertz (GHz) to 10 GHz. ### Claim 4 (depends on 2) The IC of claim 2, wherein the DUT comprises a variable-gain amplifier comprising a switched PMOS array coupled to a switched NMOS array. ### Claim 5 (depends on 1) The IC of claim 1, further comprising: an inductor-capacitor (LC) resonator configured to generate an oscillation signal; and an inverter coupled between the LC resonator and the first node and configured to output the AC signal based on the oscillation signal. ### Claim 6 (depends on 5) The IC of claim 5, wherein the LC resonator is configured to generate the oscillation signal having a frequency ranging from 24 gigahertz (GHz) to 100 GHz. ### Claim 7 (depends on 5) The IC of claim 5, wherein the DUT comprises an amplifier comprising a common-source configuration of a transistor and an inductive load element. ### Claim 8 (depends on 1) The IC of claim 1, further comprising a load circuit coupled to the second node. ### Claim 9 An integrated circuit (IC) comprising: a plurality of pads at a top surface of a semiconductor wafer; a device-under-test (DUT) configured to receive a first alternating current (AC) signal at a first node and output a second AC signal at a second node, the second AC signal being based on the first AC signal; and first and second detection circuits, wherein each of the first and second detection circuits comprises: a first gain stage coupled to a corresponding one of the first or second nodes through a first capacitive device; a second gain stage in a cascade arrangement with the first gain stage; and a low-pass filter configured to output a direct current (DC) signal to a corresponding pad of the plurality of pads, the DC signal being based on an output signal of the second gain stage. ### Claim 10 (depends on 9) The IC of claim 9, further comprising: a ring oscillator configured to generate an oscillation signal; and a low-pass filter coupled between the ring oscillator and the first node and configured to output the AC signal based on the oscillation signal, wherein the DUT comprises a variable-gain amplifier comprising a switched PMOS array coupled to a switched NMOS array. ### Claim 11 (depends on 10) The IC of claim 10, wherein the ring oscillator is configured to generate the oscillation signal having a frequency ranging from 1 gigahertz (GHz) to 10 GHz. ### Claim 12 (depends on 10) The IC of claim 10, wherein control terminals of each of the switched PMOS array and the switched NMOS array are coupled to corresponding control pads of the plurality of pads. ### Claim 13 (depends on 9) The IC of claim 9, further comprising: an inductor-capacitor (LC) resonator configured to generate an oscillation signal; and an inverter coupled between the LC resonator and the first node and configured to output the AC signal based on the oscillation signal, wherein the DUT comprises an amplifier comprising a common-source configuration of a transistor and an inductive load element. ### Claim 14 (depends on 13) The IC of claim 13, wherein the LC resonator is configured to generate the oscillation signal having a frequency ranging from 24 gigahertz (GHz) to 100 GHz. ### Claim 15 (depends on 13) The IC of claim 13, wherein the amplifier is configured to have a gain value based on a voltage received on a node coupled to a control pad of the plurality of pads. ### Claim 16 (depends on 9) The IC of claim 9, wherein the plurality of pads is positioned in a scribe line of the semiconductor wafer. ### Claim 17 A method of generating test signals, the method comprising: using a device-under-test (DUT) to receive a first alternating current (AC) signal at a first node and output a second AC signal at a second node, the second AC signal being based on the first AC signal; and using each of first and second detection circuits to: use a first gain stage coupled to a corresponding one of the first or second nodes to detect the corresponding first or second AC signal through a first capacitive device; use a second gain stage in a cascade arrangement with the first gain stage to generate an output signal based on a gain signal received from the first gain stage; and use a low-pass filter to generate a direct current (DC) signal based on the output signal of the second gain stage. ### Claim 18 (depends on 17) The method of claim 17, further comprising: using a ring oscillator to generate an oscillation signal having a frequency ranging from 1 gigahertz (GHz) to 10 GHz; and using a low-pass filter coupled between the ring oscillator and the first node and to output the AC signal based on the oscillation signal, wherein the using the DUT to output the second AC signal comprises using a variable-gain amplifier comprising a switched PMOS array coupled to a switched NMOS array. ### Claim 19 (depends on 17) The method of claim 17, further comprising: using an inductor-capacitor (LC) resonator to generate an oscillation signal having a frequency ranging from 24 gigahertz (GHz) to 100 GHz; and using an inverter coupled between the LC resonator and the first node to output the AC signal based on the oscillation signal, wherein the using the DUT to output the second AC signal comprises using an amplifier comprising a common-source configuration of a transistor and an inductive load element. ### Claim 20 (depends on 17) The method of claim 17, further comprising: using each of the first and second detection circuits to output the corresponding DC signal to a pad of a plurality of pads at a top surface of a semiconductor wafer.