# US 12,007,431 B2 · Test circuit and method for operating the same

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- Number: US 12,007,431 B2
- Document ID: US12007431B2
- Status: Granted
- Kind: B2
- Application number: 17/459,989
- Filed: 2021-08-27
- Published: 2023-03-02
- Granted: 2024-06-11
- Earliest claimed: 2021-08-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Chia-Wei Huang; Wei-Jhih Wang; Cheng-Cheng Kuo; Yuan-Yao Chang
- Web page: https://patentgrep.com/patent/US12007431B2

## CPC

- G01R 31/2831: {Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates (G01R31/318511 takes precedence; testing during manufacture H10P74/00)}
- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a wafer. The wafer includes a die, a scribe line adjacent to the die, and a test circuit adjacent to the scribe line. The test circuit includes a first switch, a second switch, and a third switch. The first switch has a first node coupled to a first device-under-test and a second node coupled to a first signal supply node. The second switch has a first node coupled to the second DUT and a second node coupled to the first signal supply node. The third switch has a first node directly coupled to the first DUT and the second DUT. The third switch has a second node coupled to a second signal supply node. The third switch selectively couples both of the first DUT and the second DUT to the second signal supply node.

## Claims

### Claim 1

A wafer, comprising:
a die;
a scribe line adjacent to the die; and
a test circuit adjacent to the scribe line, the test circuit including:
a first switch configured to turn on or turn off a first set of devices under test (DUTs) arranged in a first column;
a second switch configured to turn on or turn off a second set of DUTs arranged in a second column;
a third switch configured to simultaneously couple a first DUT of the first set of DUTs and a second DUT of the second set of DUTs to a signal supply node; and
a fourth switch configured to simultaneously couple the first DUT and the second DUT to a signal receive node, wherein the fourth switch has a node directly coupled to the first DUT, the second DUT, and the third switch, and wherein there is no switch connected between the first DUT and the second DUT.

### Claim 2 (depends on 1)

The wafer of claim 1, wherein the third switch has a node directly coupled to the first DUT and the second DUT.

### Claim 3 (depends on 1)

The wafer of claim 1, wherein there is no switch connected between a drain of the first DUT and a drain of the second DUT.

### Claim 4 (depends on 1)

The wafer of claim 1, wherein there is no switch connected between a source of the first DUT and a source of the second DUT.

### Claim 5 (depends on 1)

The wafer of claim 1, wherein gates of the first set of DUTs are coupled to the first switch.

### Claim 6 (depends on 5)

The wafer of claim 5, wherein the first DUT and a third DUT of the first set of DUTs have different electrical characteristic in response to a signal from the signal supply node, such that when the first DUT is turned on, the third DUT is turned off, or vice versa.

### Claim 7 (depends on 1)

The wafer of claim 1, wherein the first DUT and the second DUT are arranged in a row.

### Claim 8 (depends on 1)

The wafer of claim 1, wherein the test circuit is located in the scribe line.

### Claim 9 (depends on 1)

The wafer of claim 1, wherein the first DUT comprises a metal oxide semiconductor (MOS) transistor having a gate coupled to the first switch and a drain coupled to the third switch.

### Claim 10 (depends on 1)

The wafer of claim 1, wherein the second DUT comprises a MOS transistor having a gate coupled to the first switch and a drain coupled to the third switch.

### Claim 11

A method for manufacturing a test circuit, comprising:
providing a wafer having a die;
providing a first switch, a second switch, a third switch, a fourth switch, and a fifth switch;
coupling a first set of DUTs arranged in a first column to the first switch;
coupling a second set of DUTs arranged in a second column to the second switch;
coupling a drain of a first DUT of the first set of DUTs and a drain of a second DUT of the second set of DUTs to a first signal supply node through the third switch, wherein there is no switch connected between the drain of the first DUT and the drain of the second DUT;
coupling the drain of the first DUT and the drain of the second DUT to a signal receive node through the fourth switch; and
coupling a source of the first DUT and a source of the second DUT to a second signal supply node through the fifth switch.

### Claim 12 (depends on 11)

The method of claim 11, wherein there is no switch connected between the source of the first DUT and the source of the second DUT.

### Claim 13 (depends on 11)

The method of claim 11, wherein there is no switch connected between the source of the first DUT and a gate of the first DUT.

### Claim 14 (depends on 11)

The method of claim 11, wherein the first DUT and the second DUT are arranged in a row.

### Claim 15 (depends on 11)

The method of claim 11, wherein the first DUT and a third DUT (M1_2) of the first set of DUTs have different electrical characteristic such that when the first DUT is turned on, the third DUT is turned off, or vice versa.

### Claim 16

A method for testing a wafer, the wafer including a die, a scribe line adjacent to the die, and a test circuit in the scribe line, the test circuit including a first switch configured to turn on or turn off a first set of DUTs arranged in a first column, a second switch configured to turn on or turn off a second set of DUTs arranged in a second column, and a third switch configured to simultaneously couple a first DUT of the first set of DUTs and a second DUT of the second set of DUTs to a signal supply node, the method comprising:
applying a first test signal to the first DUT and the second DUT through the third switch;
switching a logic state of the first DUT through the first switch;
switching a logic state of the second DUT through the second switch; and
detecting a short circuit via determining electrical continuity between a drain of the first DUT and a drain of the second DUT.

### Claim 17 (depends on 16)

The method of claim 16, wherein the test circuit includes a fourth switch configured to simultaneously couple the first DUT and the second DUT to a signal receive node, and the method further comprising:
receiving a sensing signal from the first DUT and the second DUT through the fourth switch.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
turning on the first DUT and turning off a third DUT of the first set of DUTs through the first switch.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
turning off the first DUT and turning on the third DUT through the first switch; and
applying a second test signal to the third DUT through a fifth switch.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
applying the second test signal to a fourth DUT (M2_2) of the second set of DUTs through the fifth switch.