# US 12,007,429 B2 · Apparatus and method for managing power of test circuits

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- Number: US 12,007,429 B2
- Document ID: US12007429B2
- Status: Granted
- Kind: B2
- Application number: 17/848,972
- Filed: 2022-06-24
- Published: 2022-12-29
- Granted: 2024-06-11
- Earliest claimed: 2021-06-25
- Assignees: Ic Analytica, LLC
- Applicants: Ic Analytica, LLC
- Inventors: Patrick G. Drennan; Joseph S. Spector; Richard Wunderlich
- Web page: https://patentgrep.com/patent/US12007429B2

## CPC

- G01R 31/275: {for testing individual semiconductor components within integrated circuits}
- G01R 31/318511: {Wafer Test}
- G01R 1/07342: {the body of the probe being at an angle other than perpendicular to test object, e.g. probe card}
- G01R 31/2601: {Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence)}
- G01R 31/2856: {Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]}
- G01R 31/31721: {Power aspects, e.g. power supplies for test circuits, power saving during test (for scan test G01R31/318575)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Voltage regulators are positioned within the scribe lines. Each voltage regulator is connected to one or more chips. Selection circuitry is positioned within the scribe lines. The selection circuitry governs access to a chip being tested.

## Claims

### Claim 1

An apparatus, comprising:
a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines;
voltage regulators positioned within the scribe lines, each voltage regulator being connected to one or more test circuits, the voltage regulators being controlled by a single voltage reference signal that regulates the intended supply voltage; and
selection circuitry positioned within the scribe lines, the selection circuitry governing access to a chip being tested, the selection circuitry utilizing solely pMOS transistors to direct current from the chip being tested to a selected source measurement unit.

### Claim 2 (depends on 1)

The apparatus of claim 1 wherein current for a test circuit being tested is isolated from all other test circuits on the semiconductor wafer.