# US 12,004,436 B2 · RRAM with high work function cap > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,004,436 B2 - Document ID: US12004436B2 - Status: Granted - Kind: B2 - Application number: 17/815,582 - Filed: 2022-07-28 - Published: 2024-02-01 - Granted: 2024-06-04 - Earliest claimed: 2022-07-28 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Soon-Cheon Seo; Min Gyu Sung; Takashi Ando; Chanro Park; Mary Claire Micaller Silvestre; Xuefeng Liu - Web page: https://patentgrep.com/patent/US12004436B2 ## CPC - H10N 70/20: Multistable switching devices, e.g. memristors - H10N 70/8833: {Binary metal oxides, e.g. TaOx} - H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays} - H10N 70/011: {Manufacture or treatment of multistable switching devices} - H10N 70/023: {by chemical vapor deposition, e.g. MOCVD, ALD} - H10N 70/061: {Shaping switching materials} - H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography} - H10N 70/066: {by filling of openings, e.g. damascene method} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10N 70/841: {Electrodes} - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Embodiments of present invention provide a resistive random-access memory (RRAM) cell. The RRAM cell includes a bottom electrode; a metal oxide layer, the metal oxide layer having a central portion that is in direct contact with the bottom electrode, a peripheral portion that is nonplanar with the central portion, and a vertical portion between the central portion and the peripheral portion; and a top electrode directly above the metal oxide layer. A method of manufacturing the RRAM cell is also provided. ## Claims ### Claim 1 A resistive random-access memory (RRAM) cell comprising: a bottom electrode; a metal oxide layer, the metal oxide layer having a central portion that is in direct contact with the bottom electrode, a peripheral portion that is nonplanar with the central portion, and a vertical portion between the central portion and the peripheral portion; a top electrode directly above the metal oxide layer; and a dielectric layer, wherein an outer surface of the vertical portion of the metal oxide layer is directly adjacent to the dielectric layer. ### Claim 2 (depends on 1) The RRAM cell of claim 1, wherein the bottom electrode has a top surface, a bottom surface, and a sidewall between the top surface and the bottom surface, the sidewall of the bottom electrode being surrounded by the dielectric layer. ### Claim 3 (depends on 1) The RRAM cell of claim 1, wherein the top electrode is on top of the central portion and the peripheral portion of the metal oxide layer and directly adjacent to an inner surface of the vertical portion of the metal oxide layer. ### Claim 4 (depends on 1) The RRAM cell of claim 1, wherein the bottom electrode has a first thickness and the dielectric layer has a second thickness, and wherein the first thickness is less than the second thickness. ### Claim 5 (depends on 4) The RRAM cell of claim 4, wherein a portion of the top electrode is in direct contact with an inner surface of the vertical portion of the metal oxide layer and is horizontally surrounded by the dielectric layer. ### Claim 6 (depends on 5) The RRAM cell of claim 5, wherein the peripheral portion of the metal oxide layer is directly above the dielectric layer and the central portion of the metal oxide layer is at a level below a top surface of the dielectric layer. ### Claim 7 A resistive random-access memory (RRAM) cell comprising: a bottom electrode; a metal oxide layer, the metal oxide layer having a central portion that is in direct contact with the bottom electrode, a peripheral portion that is nonplanar with the central portion, and a vertical portion between the central portion and the peripheral portion; a top electrode directly above the metal oxide layer; a dielectric layer underneath the peripheral portion of the metal oxide layer; and a bottom contact stud surrounded by the dielectric layer and in direct contact with the bottom electrode, wherein the bottom electrode and the bottom contact stud have a same contact area. ### Claim 8 (depends on 7) The RRAM cell of claim 7, wherein the bottom electrode is fully encapsuled by the bottom contact stud and the metal oxide layer. ### Claim 9 (depends on 7) The RRAM cell of claim 7, wherein the central portion of the metal oxide layer is at a level above a top surface of the dielectric layer. ### Claim 10 (depends on 7) The RRAM cell of claim 7, wherein a portion of the top electrode is in direct contact with an outer surface of the vertical portion of the metal oxide layer. ### Claim 11 A method of forming a semiconductor structure comprising: receiving a contact structure having a contact area; forming a bottom electrode on top of the contact area; forming a metal oxide layer, the metal oxide layer having a central portion directly above and in contact with the bottom electrode and a peripheral portion above a dielectric layer, wherein the peripheral portion of the metal oxide layer is nonplanar with the central portion of the metal oxide layer; forming a top electrode layer above the metal oxide layer; and patterning the top electrode layer and the metal oxide layer, wherein the dielectric layer is above the contact structure and has an opening exposing the contact area of the contact structure, wherein forming the bottom electrode comprises selectively forming the bottom electrode on top of the exposed contact area inside the opening, the bottom electrode being surrounded by the dielectric layer. ### Claim 12 (depends on 11) The method of claim 11, wherein forming the metal oxide layer comprises forming the central portion of the metal oxide layer directly on top of the bottom electrode inside the opening and the peripheral portion of the metal oxide on top of the dielectric layer outside the opening.