# US 12,004,396 B2 · Display panel and display device for IVL testing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,004,396 B2 - Document ID: US12004396B2 - Status: Granted - Kind: B2 - Application number: 17/954,377 - Filed: 2022-09-28 - Published: 2023-01-19 - Granted: 2024-06-04 - Earliest claimed: 2022-09-28 - Assignees: Boe Technology Group Co., Ltd. - Applicants: Boe Technology Group Co., Ltd. - Inventors: Zhijian Zhu; Pengcheng Lu; Yu Ao; Yunlong Li; Yuanlan Tian - Web page: https://patentgrep.com/patent/US12004396B2 ## CPC - H10K 59/131: Interconnections, e.g. wiring lines or terminals - G09G 3/006: {Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309)} - H10K 71/70: Testing, e.g. accelerated lifetime tests - H10P 74/00: Testing or measuring during manufacture or treatment of wafers, substrates or devices - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10K 59/1213: {the pixel elements being TFTs} - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A display panel includes: a silicon-based substrate, a driving layer, a first electrode layer, an organic light emitting layer, a second electrode layer and a plurality of pads. Where, the display signal access pad is configured to access the display signal during a display phase, the test signal access pad at least includes a first group of test phase access pads, and the first group of test phase access pads includes a first pad and a second pad, the first pad is electrically connected with the electrode ring, and the second pad is electrically connected with the silicon-based substrate. ## Claims ### Claim 1 A display panel, comprising: a silicon-based substrate, comprising a display region and a peripheral region surrounding the display region; a driving layer, formed in the silicon-based substrate, and comprising a plurality of first transistors located in the display region; a first electrode layer, disposed on a side of the driving layer away from the silicon-based substrate, and comprising a plurality of first electrodes located in the display region, wherein each of the first electrodes is electrically connected to each of the first transistors; an organic light emitting layer, disposed on a side of the first electrode layer away from the driving layer; a second electrode layer, disposed on a side of the organic light emitting layer away from the driving layer; and a plurality of pads, located in the peripheral region on at least one side of the display region, wherein the plurality of pads comprises a display signal access pad and a test signal access pad; the display signal access pad is arranged in a first direction, the display signal access pad comprises a first end portion and a second end portion in the first direction; the test signal access pad is located in a regions for the first end portion and the second end portion of the display signal access pad in the first direction; the test signal access pad comprises at least a first pad and a third pad, the first pad and the third pad do not overlap in the first direction; and the third pad overlaps with the display signal access pad in the first direction. ### Claim 2 (depends on 1) The display panel according to claim 1, wherein an area of the first pad is smaller than an area of the display signal access pad. ### Claim 3 (depends on 1) The display panel according to claim 1, wherein an area of the first pad is smaller than an area of the third pad. ### Claim 4 (depends on 1) The display panel according to claim 1, wherein spacing between the third pad and an edge of the silicon-based substrate is smaller than spacing between the first pad and the edge of the silicon-based substrate in a second direction perpendicular to the first direction. ### Claim 5 (depends on 1) The display panel according to claim 1, wherein the test signal access pad comprises a first group of test phase access pads, the first group of test phase access pads comprises the first pad and a second pad; the second electrode layer comprises a second electrode located in the display region and an electrode ring located in the peripheral region, the electrode ring is configured to surround the second electrode and is connected to the second electrode; the first pad is electrically connected with the electrode ring, and the second pad is electrically connected with the silicon-based substrate. ### Claim 6 (depends on 5) The display panel according to claim 5, wherein the test signal access pad further comprises a second group of test phase access pads, the second group of test phase access pads comprise the third pad and a fourth pad; in the first direction, the second pad and the fourth pad do not overlap, and the fourth pad overlaps with the display signal access pad; the third pad is electrically connected to the electrode ring, and the fourth pad is electrically connected to the silicon-based substrate. ### Claim 7 (depends on 6) The display panel according to claim 6, wherein the first pad and the third pad are located at the first end portion of the display signal access pad, and the second pad and the fourth pad are located at the second end portion of the display signal access pad. ### Claim 8 (depends on 7) The display panel according to claim 7, wherein the third pad and the fourth pad are respectively arranged adjacent to the display signal access pad. ### Claim 9 (depends on 6) The display panel according to claim 6, wherein the peripheral region comprises a bonding area, and the third pad, the fourth pad and a plurality of display signal access pads are located in the bonding area. ### Claim 10 (depends on 6) The display panel according to claim 6, wherein the display panel is provided with one first pad and one second pad. ### Claim 11 (depends on 6) The display panel according to claim 6, wherein the third pad is electrically connected to the first pad, and the fourth pad is electrically connected to the second pad. ### Claim 12 (depends on 6) The display panel according to claim 6, wherein the driving layer further comprises: a connection line, being electrically connected to the second pad and the fourth pad; and a plurality of detection lines, being connected to the connection line, and each of the detection lines is electrically connected to active regions of a row of first transistors respectively. ### Claim 13 (depends on 6) The display panel according to claim 6, wherein the display panel further comprises: a first packaging layer, disposed on a side of the second electrode layer away from the organic light emitting layer; a color film layer, disposed on a side of the first packaging layer away from the second electrode layer; a second packaging layer, disposed on a side of the color film layer away from the first packaging layer, wherein the third pad and the fourth pad are exposed from the second packaging layer. ### Claim 14 (depends on 5) The display panel according to claim 5, wherein the first pad is electrically connected to the electrode ring through a conducting wire. ### Claim 15 (depends on 5) The display panel according to claim 5, wherein each of the first transistors comprises an active region formed in the silicon-based substrate, two doped regions located in the active region, a channel region located between the two doped regions, and a gate electrode located on the channel region, the two doped regions respectively form a first pole and a second pole, and the second pad is electrically connected to the active region of each of the first transistors. ### Claim 16 (depends on 15) The display panel according to claim 15, wherein the driving layer comprises: a gate insulating layer, disposed on the channel region on a side of the silicon-based substrate; a gate layer, disposed on a side of the gate insulating layer away from the silicon-based substrate; a first planarization layer, disposed on a side of the silicon-based substrate and configured to cover the gate insulating layer and the gate layer; a first conductive layer, disposed on a side of the first planarization layer away from the silicon-based substrate; a dielectric layer, disposed on a side of the first planarization layer away from the silicon-based substrate and configured to cover the first conductive layer; a second conductive layer, disposed on a side of the dielectric layer away from the silicon-based substrate; and a second planarization layer, disposed on a side of the dielectric layer away from the silicon-based substrate and configured to cover the second conductive layer, wherein the first electrode layer is located on a side of the second planarization layer away from the silicon-based substrate. ### Claim 17 (depends on 5) The display panel according to claim 5, wherein the display panel further comprises: a second transistor, formed in the peripheral region of the silicon-based substrate, and comprising an active region formed in the silicon-based substrate, two doped regions located in the active region, a channel region located between the two doped regions, and a gate electrode located on the channel region, wherein the two doped regions respectively form a first pole and a second pole; the second pole of the second transistor is electrically connected to the electrode ring, and the first pad is electrically connected to the first pole and the gate electrode of the second transistor. ### Claim 18 (depends on 1) The display panel according to claim 1, wherein the test signal access pad and the first electrode are arranged in the same layer. ### Claim 19 A display device, comprising a display panel, wherein the display panel comprises: a silicon-based substrate, comprising a display region and a peripheral region surrounding the display region; a driving layer, formed in the silicon-based substrate, and comprising a plurality of first transistors located in the display region; a first electrode layer, disposed on a side of the driving layer away from the silicon-based substrate, and comprising a plurality of first electrodes located in the display region, wherein each of the first electrodes is electrically connected to each of the first transistors; an organic light emitting layer, disposed on a side of the first electrode layer away from the driving layer; a second electrode layer, disposed on a side of the organic light emitting layer away from the driving layer; and a plurality of pads, located in the peripheral region on at least one side of the display region, wherein the plurality of pads comprises a display signal access pad and a test signal access pad; the display signal access pad is arranged in a first direction, the display signal access pad comprises a first end portion and a second end portion in the first direction; the test signal access pad is located in a regions for the first end portion and the second end portion of the display signal access pad in the first direction; the test signal access pad comprises at least a first pad and a third pad, the first pad and the third pad do not overlap in the first direction; and the third pad overlaps with the display signal access pad in the first direction.