# US 12,004,354 B2 · Memory arrays comprising vertically-alternating tiers of insulative material and memory cells and methods of forming a memory array comprising memory cells individually comprising a transistor and a capacitor

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- Number: US 12,004,354 B2
- Document ID: US12004354B2
- Status: Granted
- Kind: B2
- Application number: 17/235,343
- Filed: 2021-04-20
- Published: 2021-08-05
- Granted: 2024-06-04
- Earliest claimed: 2017-06-29
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Durai Vishak Nirmal Ramaswamy
- Web page: https://patentgrep.com/patent/US12004354B2

## CPC

- H10B 53/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/05: {Making the transistor}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/48: {Data lines or contacts therefor}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10D 1/692: {Electrodes}
- H10D 1/716: {having vertical extensions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 20/43: Layouts of interconnections
- H10B 51/10: characterised by the top-view layout
- H10B 51/30: characterised by the memory core region
- H10B 53/10: characterised by the top-view layout
- H10B 53/30: characterised by the memory core region
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 50/283: {by chemical means}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. An access-line pillar extends elevationally through the vertically-alternating tiers. The gate of individual of the transistors in different of the memory-cell tiers comprises a portion of the elevationally-extending access-line pillar. Other embodiments, including method, are disclosed.

## Claims

### Claim 1

A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor comprising first and second source/drain regions having a channel region there-between, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; and
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;
a pair of laterally-spaced access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual ones of the channel regions that are in different ones of the memory-cell tiers, portions of the access-line pillars in the different memory-cell tiers comprising a pair of gates on the opposite sides of the individual channel regions of individual ones of the transistors in the different memory-cell tiers;
a sense line electrically coupled to individual ones of multiple of the second source/drain regions;
the individual transistors comprising a gate insulator that is laterally between the gate and the channel region, the gate insulator being laterally between and separating the gate and the first source/drain region from physically contacting one another, the gate insulator being laterally between and separating the gate and the second source/drain region from physically contacting one another; and
the first and second source/drain regions each have a vertical side that is directly against both of the channel region and the gate insulator, a greater quantity of each of the vertical sides of the first and second source/drain regions being directly against the gate insulator than is directly against the channel region.

### Claim 2 (depends on 1)

The array of claim 1 comprising a horizontally-extending conductive strap that directly electrically couples the pair of access-line pillars together.

### Claim 3 (depends on 2)

The array of claim 2 comprising a horizontal longitudinally-elongated conductive line directly electrically coupled to the conductive strap of multiple of the pairs of access-line pillars.

### Claim 4 (depends on 2)

The array of claim 2 wherein the conductive strap is above the pair of access-line pillars.

### Claim 5 (depends on 4)

The array of claim 4 comprising a horizontal longitudinally-elongated conductive line directly electrically coupled to the conductive strap of multiple of the pairs of access-line pillars.

### Claim 6

A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor comprising first and second source/drain regions having a channel region there-between, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; and
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;
a pair of laterally-spaced access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual ones of the channel regions that are in different ones of the memory-cell tiers, portions of the access-line pillars in the different memory-cell tiers comprising a pair of gates on the opposite sides of the individual channel regions of individual ones of the transistors in the different memory-cell tiers;
a sense line electrically coupled to individual ones of multiple of the second source/drain regions along a y-direction;
a conductive strap that is longitudinally-elongated along the y-direction, the conductive strap directly electrically coupling the pair of access-line pillars together; and
two conductive lines that are longitudinally-elongated along an x-direction that is orthogonal to the y-direction, one of the two conductive lines directly electrically coupling together a first series of the conductive straps of multiple of the pairs of access-line pillars that alternate relative to one another along the x-direction, the other of the two conductive lines directly electrically coupling together a second series of the conductive straps of multiple of the pairs of access-line pillars that alternate relative to one another and to the first series of the conductive straps along the x-direction.

### Claim 7

A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor comprising first and second source/drain regions having a channel region there-between, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; and
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;
a pair of laterally-spaced access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual ones of the channel regions that are in different ones of the memory-cell tiers, portions of the access-line pillars in the different memory-cell tiers comprising a pair of gates on the opposite sides of the individual channel regions of individual ones of the transistors in the different memory-cell tiers;
a sense line electrically coupled to individual ones of multiple of the second source/drain regions;
a conductive strap above the pair of access-line pillars that is longitudinally-elongated and directly electrically couples the pair of access-line pillars together;
a conductive line above the conductive strap that is longitudinally-elongated along an x-direction and that directly electrically couples to the conductive strap of multiple of the pairs of access-line pillars; and
a conductive line below the conductive line that is above the conductive strap and that is longitudinally-elongated along a y-direction that is orthogonal to the x-direction, the conductive line that is longitudinally-elongated in the y-direction directly electrically coupling together individual ones of the second capacitor electrodes.