# US 12,004,353 B2 · Semiconductor devices including a contact structure that contacts a dummy channel structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,004,353 B2 - Document ID: US12004353B2 - Status: Granted - Kind: B2 - Application number: 18/299,150 - Filed: 2023-04-12 - Published: 2023-09-28 - Granted: 2024-06-04 - Earliest claimed: 2018-12-11 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Joo Won Park; Kyeong Jin Park; Kwang Soo Kim - Web page: https://patentgrep.com/patent/US12004353B2 ## CPC - H10B 43/10: characterised by the top-view layout - H10B 43/40: characterised by the peripheral circuit region - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/42: Vias, e.g. via plugs - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers. ## Claims ### Claim 1 A semiconductor device comprising: a substrate having a cell region and a connection region adjacent to the cell region; a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate; a source mold layer between the substrate and the stacked structure in the connection region; an alternate conductive line between the substrate and the stacked structure in the cell region; a plurality of cell channel structures in the cell region, the plurality of cell channel structures extending into the alternate conductive line while passing through the stacked structure; a plurality of extension structures in the connection region, the plurality of extension structures extending into the source mold layer while passing through the stacked structure; and a contact structure that is among the plurality of extension structures in the connection region while being in direct contact with one of the plurality of electrode layers, wherein each of the plurality of cell channel structures comprises: a channel pattern, and an information storage pattern outside the channel pattern, wherein the channel pattern is electrically connected to the alternate conductive line, and wherein the plurality of extension structures are not electrically connected to the alternate conductive line. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the alternate conductive line is at a level substantially equal to that of the source mold layer, and wherein the channel pattern passes through the alternate conductive line and has a lower surface that is below a lower surface of the alternate conductive line. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the alternate conductive line has a thickness substantially equal to that of the source mold layer, and wherein the channel pattern is between spaced-apart portions of the alternate conductive line. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the alternate conductive line is in direct contact with the channel pattern while passing through a side surface of the information storage pattern. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, further comprising: a first portion that is between the alternate conductive line and the stacked structure; and a second portion that is between the substrate and the stacked structure and extends from the first portion, wherein the second portion is in direct contact with side surfaces of the alternate conductive line and the source mold layer. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein the second portion extends between the alternate conductive line and the source mold layer. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the second portion protrudes toward the substrate. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the contact structure is in direct contact with at least one of the plurality of extension structures adjacent thereto. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the contact structure comprises: a contact plug; and a contact spacer surrounding an outer side of the contact plug. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein: a width of an upper region of the contact structure is greater than that of a lower region of the contact structure; the upper region of the contact structure is in direct contact with at least one of the plurality of extension structures adjacent thereto; and the lower region of the contact structure is spaced apart from the at least one of the plurality of extension structures adjacent thereto. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the contact structure is in direct contact with four of the plurality of extension structures that are spaced apart from one another. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein the contact structure comprises a protrusion penetrating into one of the plurality of extension structures adjacent thereto. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the protrusion overlaps with a center of the one of the plurality of extension structures. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein each of the extension structures includes an insulation layer. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein: each of the plurality of cell channel structures further comprises a core pattern; and the contact structure is in direct contact with the insulation layer of the plurality of extension structures. ### Claim 16 (depends on 1) The semiconductor device according to claim 1, further comprising: a plurality of transistors; and a plurality of peripheral circuit interconnections connected to at least one of the plurality of transistors, wherein the plurality of transistors and the plurality of peripheral circuit interconnections are disposed below the plurality of extension structures. ### Claim 17 (depends on 1) The semiconductor device according to claim 1, further comprising: an interlayer insulating layer in the connection region, wherein each of the plurality of electrode layers comprises a pad portion extending into the connection region, wherein the interlayer insulating layer is on the pad portion, wherein the contact structure passes through the interlayer insulating layer to be in direct contact with the pad portion. ### Claim 18 (depends on 17) The semiconductor device according to claim 17, wherein one of the plurality of extension structures adjacent to the contact structure passes through the pad portion. ### Claim 19 A semiconductor device comprising: a substrate having a cell region and a connection region adjacent to the cell region; a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate; a source mold layer between the substrate and the stacked structure in the connection region; an alternate conductive line between the substrate and the stacked structure in the cell region; a plurality of cell channel structures in the cell region, the plurality of cell channel structures extending into the alternate conductive line while passing through the stacked structure; a plurality of extension structures in the connection region, the plurality of extension structures extending into the source mold layer while passing through the stacked structure; and a contact structure that is among the plurality of extension structures in the connection region while being in direct contact with one of the plurality of electrode layers, wherein each of the plurality of cell channel structures comprises a channel pattern electrically connected to the alternate conductive line, and wherein the plurality of extension structures are not electrically connected to the alternate conductive line. ### Claim 20 A semiconductor device comprising: a substrate having a cell region and a connection region adjacent to the cell region; a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate; a source mold layer between the substrate and the stacked structure in the connection region; an alternate conductive line between the substrate and the stacked structure in the cell region; a plurality of cell channel structures in the cell region, wherein the alternate conductive line is on opposite sidewalls of each of the plurality of cell channel structures; a plurality of extension structures in the connection region, the plurality of extension structures extending into the source mold layer while passing through the stacked structure; and a contact structure that is among the plurality of extension structures in the connection region while being in direct contact with one of the plurality of electrode layers, wherein each of the plurality of cell channel structures comprises a channel pattern electrically connected to the alternate conductive line, and wherein the plurality of extension structure are not electrically connected to the alternate conductive line.