# US 12,004,351 B2 · Integrated assemblies, and methods of forming integrated assemblies

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- Number: US 12,004,351 B2
- Document ID: US12004351B2
- Status: Granted
- Kind: B2
- Application number: 17/869,732
- Filed: 2022-07-20
- Published: 2022-11-17
- Granted: 2024-06-04
- Earliest claimed: 2020-08-04
- Applicants: Lodestar Licensing Group LLC
- Inventors: S. M. Istiaque Hossain; Prakash Rau Mokhna Rau; Arun Kumar Dhayalan; Damir Fazil; Joel D. Peterson; Anilkumar Chandolu; Albert Fayrushin; George Matamis; Christopher Larsen; Rokibul Islam
- Web page: https://patentgrep.com/patent/US12004351B2

## CPC

- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

## Claims

### Claim 1

An integrated assembly, comprising:
a first deck having first memory cell levels alternating with first insulative levels;
a second deck over the first deck, the second deck having second memory cell levels alternating with second insulative levels; and
an intermediate level between the first and second decks, the intermediate level comprising a buffer region, the buffer region having a vertical thickness which is approximately equivalent to at least a combined vertical thickness of two of the first memory cell levels and one of the first insulative levels, and the buffer region comprising a composition of conductive material.

### Claim 2 (depends on 1)

The integrated assembly of claim 1 wherein the buffer region comprises a composition different from the first and second insulative levels.

### Claim 3 (depends on 1)

The integrated assembly of claim 1 wherein the buffer region comprises a composition different from the first and second memory cell levels.

### Claim 4

A method of forming an integrated assembly, comprising:
forming a first stack of alternating first and second tiers, the first and second tiers comprising a first material and an insulative second material, respectively;
forming a trench to extend through an uppermost portion of the first stack;
forming buffer material within the trench;
forming a first opening to extend through the first stack;
after forming the first opening, forming a second stack of alternating third and fourth tiers over the first stack, the third and fourth tiers comprising a third material and an insulative fourth material, respectively;
forming a second opening to extend through the second stack to the first opening; and
forming a channel-material-pillar within the first and second openings.

### Claim 5 (depends on 4)

The method of claim 4 further comprising replacing at least some of the first and third materials with one or more conductive materials.

### Claim 6 (depends on 4)

The method of claim 4 wherein the forming of the channel-material-pillar comprises forming channel material within both of the first and second openings in a single step.

### Claim 7 (depends on 4)

The method of claim 4 further comprising:
forming a first region of the channel-material-pillar within the first opening;
forming sacrificial material over the first region of the channel-material-pillar; and
forming a second region of the channel-material-pillar within the second opening.

### Claim 8 (depends on 4)

The method of claim 4 wherein the first and third materials are a same composition as one another.

### Claim 9 (depends on 4)

The method of claim 4 wherein the second and fourth materials are a same composition as one another.

### Claim 10

A method of forming an integrated assembly, comprising:
forming a first stack of alternating first and second tiers, the first and second tiers comprising a first material and an insulative second material, respectively, a portion of the first stack being within a memory-block-location;
forming first openings to extend through the first stack;
forming a trench to extend through an uppermost portion of the first stack;
forming buffer material within the trench;
forming a second stack of alternating third and fourth tiers over the first stack and the buffer material, the third and fourth tiers comprising a third material and an insulative fourth material, respectively;
after forming the first openings, forming second openings through the second stack to the first openings to form pillar openings which extend through the first and second stacks; and
forming slits along edges of the memory-block-location.

### Claim 11 (depends on 10)

The method of claim 10 further comprising removing the first and third materials with one or more etchants flowed into the slits.

### Claim 12 (depends on 11)

The method of claim 11 wherein the removal of the first and third materials comprises forming voids within the first and third tiers.

### Claim 13 (depends on 12)

The method of claim 12 further comprising forming one or more conductive materials within the voids.

### Claim 14 (depends on 10)

The method of claim 10 further comprising forming cell-material-pillars within the pillar openings.

### Claim 15 (depends on 14)

The method of claim 14 wherein the cell-material-pillars include charge-blocking material, charge-storage material, tunneling material and channel material.

### Claim 16

An integrated assembly, comprising:
a first deck having first memory cell levels alternating with first insulative levels;
a second deck over the first deck, the second deck having second memory cell levels alternating with second insulative levels; and
an intermediate level between the first and second decks, the intermediate level comprising a buffer region, the buffer region having a vertical thickness which is approximately equivalent to at least a combined vertical thickness of two of the first memory cell levels and one of the first insulative levels, and the buffer region comprises a composition of semiconductive material.

### Claim 17

An integrated assembly, comprising:
a first deck having first memory cell levels alternating with first insulative levels;
a second deck over the first deck, the second deck having second memory cell levels alternating with second insulative levels; and
an intermediate level between the first and second decks, the intermediate level comprising a buffer region, the buffer region having a vertical thickness which is approximately equivalent to at least a combined vertical thickness of two of the first memory cell levels and one of the first insulative levels, and the buffer region comprises a composition of metal.