# US 12,004,347 B2 · Three-dimensional memory device including self-aligned drain-select-level isolation structures and method of making thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,004,347 B2 - Document ID: US12004347B2 - Status: Granted - Kind: B2 - Application number: 17/237,476 - Filed: 2021-04-22 - Published: 2022-10-27 - Granted: 2024-06-04 - Earliest claimed: 2021-04-22 - Assignees: SanDisk Technologies LLC - Applicants: Sandisk Technologies LLC - Inventors: Nobuyuki Fujimura; Satoshi Shimizu; Takumi Moriyama - Web page: https://patentgrep.com/patent/US12004347B2 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/10: characterised by the top-view layout - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/10: characterised by the top-view layout - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10B: ELECTRONIC MEMORY DEVICES ## Abstract An alternating stack of insulating layers and spacer material layers is formed over a substrate. A plurality of arrays of memory opening fill structures is formed through the alternating stack. A plurality of dielectric plates is formed, which laterally surrounds a respective array of memory opening fill structures. Self-aligned drain-select-level isolation structures are formed between a respective neighboring pair of arrays of memory opening fill structures through gaps between neighboring pairs of the dielectric plates into a subset of layers within the alternating stack. Drain side select gate electrodes are provided from a divided subset of the spacer material layers. ## Claims ### Claim 1 A three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers; a plurality of arrays of memory openings vertically extending through the alternating stack; a plurality of arrays of memory opening fill structures located in the plurality of arrays of memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements, and each array of memory opening fill structures comprises a respective set of rows of memory opening fill structures that are arranged along a first horizontal direction, and the plurality of arrays of memory opening fill structures are laterally spaced apart from each other along a second horizontal direction; a plurality of dielectric plates laterally surrounding a respective array of memory opening fill structures, wherein each of the plurality of dielectric plates has an outer sidewall that is laterally spaced from a most proximal memory opening fill structure within a respective array of memory opening fill structures by a lateral offset distance; drain-select-level isolation structures located between a respective neighboring pair of arrays of memory opening fill structures; and a contact-level dielectric layer overlying the plurality of dielectric plates, wherein top surfaces of the drain-select-level isolation structures are located within a same horizontal plane as a top surface of the contact-level dielectric layer, wherein: the lateral offset distance comprises a uniform lateral offset distance; each of the drain-select-level isolation structures comprises a respective pair of lengthwise sidewalls that are vertically coincident with a subset of sidewall segments of a respective neighboring pair of dielectric plates of the plurality of dielectric plates; each of the drain-select-level isolation structures comprises a pair of straight sidewalls that laterally extend along the first horizontal direction; and each straight sidewall in the pair of straight sidewalls contacts a top surface of a respective one of the plurality of dielectric plates. ### Claim 2 (depends on 1) The three-dimensional memory device of claim 1, wherein: bottom surfaces of the plurality of dielectric plates are located within a same horizontal plane as a bottom surface of the contact-level dielectric layer; and each of the memory opening fill structures comprises a memory film having an outer sidewall in contact with a respective one of the dielectric plates, a respective vertical semiconductor channel and a respective drain region located over the respective vertical semiconductor channel. ### Claim 3 A three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers; a plurality of arrays of memory openings vertically extending through the alternating stack; a plurality of arrays of memory opening fill structures located in the plurality of arrays of memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements, and each array of memory opening fill structures comprises a respective set of rows of memory opening fill structures that are arranged along a first horizontal direction, and the plurality of arrays of memory opening fill structures are laterally spaced apart from each other along a second horizontal direction; a plurality of dielectric plates laterally surrounding a respective array of memory opening fill structures, wherein each of the plurality of dielectric plates has an outer sidewall that is laterally spaced from a most proximal memory opening fill structure within a respective array of memory opening fill structures by a lateral offset distance; and drain-select-level isolation structures located between a respective neighboring pair of arrays of memory opening fill structures, wherein: the lateral offset distance comprises a uniform lateral offset distance; each of the drain-select-level isolation structures comprises a respective pair of lengthwise sidewalls that are vertically coincident with a subset of sidewall segments of a respective neighboring pair of dielectric plates of the plurality of dielectric plates; and the subset of sidewall segments of the respective neighboring pair of dielectric plates of the plurality of dielectric plates comprises: a first lengthwise sidewall that comprises a contiguous set of multiple vertically straight and laterally convex sidewall segments of one of the respective neighboring pair of dielectric plates; and a second lengthwise sidewall that comprises a contiguous set of multiple vertically straight and laterally convex sidewall segments of another of the respective neighboring pair of dielectric plates. ### Claim 4 A three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers; a plurality of arrays of memory openings vertically extending through the alternating stack; a plurality of arrays of memory opening fill structures located in the plurality of arrays of memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements, and each array of memory opening fill structures comprises a respective set of rows of memory opening fill structures that are arranged along a first horizontal direction, and the plurality of arrays of memory opening fill structures are laterally spaced apart from each other along a second horizontal direction; a plurality of dielectric plates laterally surrounding a respective array of memory opening fill structures, wherein each of the plurality of dielectric plates has an outer sidewall that is laterally spaced from a most proximal memory opening fill structure within a respective array of memory opening fill structures by a lateral offset distance; and drain-select-level isolation structures located between a respective neighboring pair of arrays of memory opening fill structures, wherein each of the drain-select-level isolation structures comprises a respective pair of laterally undulating lengthwise sidewalls including a respective contiguous set of vertically straight and laterally concave sidewall segments that are adjoined to each other. ### Claim 5 (depends on 4) The three-dimensional memory device of claim 4, wherein each of the respective pair of laterally undulating lengthwise sidewalls comprises: an upper surface portion contacting a laterally-undulating lengthwise sidewall of one of the plurality of dielectric plates; and a lower surface portion contacting at least one laterally-undulating lengthwise sidewall of one or more of the insulating layers. ### Claim 6 (depends on 4) The three-dimensional memory device of claim 4, wherein each of the at least one laterally-undulating lengthwise sidewall of one or more of the insulating layers comprises a respective contiguous set of vertically straight and laterally concave sidewall segments of a respective insulating layer that are adjoined to each other. ### Claim 7 A three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers; a plurality of arrays of memory openings vertically extending through the alternating stack; a plurality of arrays of memory opening fill structures located in the plurality of arrays of memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements, and each array of memory opening fill structures comprises a respective set of rows of memory opening fill structures that are arranged along a first horizontal direction, and the plurality of arrays of memory opening fill structures are laterally spaced apart from each other along a second horizontal direction; a plurality of dielectric plates laterally surrounding a respective array of memory opening fill structures, wherein each of the plurality of dielectric plates has an outer sidewall that is laterally spaced from a most proximal memory opening fill structure within a respective array of memory opening fill structures by a lateral offset distance; and drain-select-level isolation structures located between a respective neighboring pair of arrays of memory opening fill structures, wherein: each of the memory opening fill structures comprises a respective dielectric cap structure overlying the respective vertical stack of memory elements; each of the plurality of dielectric plates contacts and laterally surrounds each dielectric cap structure located within a respective array of memory opening fill structures of the plurality of arrays of memory opening fill structures; and a total number of openings through each of the plurality of dielectric plates is the same as a total number of memory opening fill structures within the respective array of memory opening fill structures. ### Claim 8 A three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers; a plurality of arrays of memory openings vertically extending through the alternating stack; a plurality of arrays of memory opening fill structures located in the plurality of arrays of memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements, and each array of memory opening fill structures comprises a respective set of rows of memory opening fill structures that are arranged along a first horizontal direction, and the plurality of arrays of memory opening fill structures are laterally spaced apart from each other along a second horizontal direction; a plurality of dielectric plates laterally surrounding a respective arra of memory opening fill structures, wherein each of the plurality of dielectric plates has an outer sidewall that is laterally spaced from a most proximal memory opening fill structure within a respective array of memory opening fill structures by a lateral offset distance; drain-select-level isolation structures located between a respective neighboring pair of arrays of memory opening fill structures; support pillar structures vertically extending through a subset of layers within the alternating stack; and discrete annular dielectric spacers laterally surrounding a top end of a respective one of the support pillar structures, comprising a same dielectric material as the plurality of dielectric plates, and having a uniform lateral distance between an outer sidewall and an inner sidewall that is the same as the uniform lateral offset distance. ### Claim 9 A three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers; a plurality of arrays of memory openings vertically extending through the alternating stack; a plurality of arrays of memory opening fill structures located in the plurality of arrays of memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements, and each array of memory opening fill structures comprises a respective set of rows of memory opening fill structures that are arranged along a first horizontal direction, and the plurality of arrays of memory opening fill structures are laterally spaced apart from each other along a second horizontal direction; a plurality of dielectric plates laterally surrounding a respective array of memory opening fill structures, wherein each of the plurality of dielectric plates has an outer sidewall that is laterally spaced from a most proximal memory opening fill structure within a respective array of memory opening fill structures bar a lateral offset distance; drain-select-level isolation structures located between a respective neighboring pair of arrays of memory opening fill structures; additional alternating stacks of additional insulating layers and additional electrically conductive layers that are laterally spaced apart from the alternating stack by a pair of line trenches that laterally extend along the first horizontal direction; and a pair of line trench fill structures comprising a respective dielectric material portion contacting a sidewall of the alternating stack and a sidewall of one of the additional alternating stacks, wherein additional memory opening fill structures vertically extend through the additional alternating stacks.