# US 12,004,345 B2 · Semiconductor with extended life time flash memory and fabrication method thereof

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- Number: US 12,004,345 B2
- Document ID: US12004345B2
- Status: Granted
- Kind: B2
- Application number: 17/538,000
- Filed: 2021-11-30
- Published: 2022-08-04
- Granted: 2024-06-04
- Earliest claimed: 2021-02-01
- Assignees: Hon Hai Precision Industry Co., Ltd.
- Applicants: Hon Hai Precision Industry Co., Ltd.
- Inventors: Chung-Yi Chen
- Web page: https://patentgrep.com/patent/US12004345B2

## CPC

- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10B 41/10: characterised by the top-view layout
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/68: Floating-gate IGFETs
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10W 90/00: Package configurations
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor with 3D flash memory storing cells giving an extended life time includes a stack structure in each storing cell, a receiving space crossing through the stack structure, a blocking layer, at least one floating gate layer, and a channel layer. The stack structure includes at least one control gate layer, at least two dielectric layers, and at least one erasing layer. The receiving space comprises a first receiving portion communicating with several second receiving portions. The first receiving portion crosses through the stack structure and the second receiving portions are coplanar with the control gate layer. The blocking layer insulates the floating gate layer from the control gate layers. The erasing layer and floating gate layer form a passageway for electrons when data erasure is required in the semiconductor. A method for fabricating the semiconductor is also disclosed.

## Claims

### Claim 1

A method for fabricating a semiconductor comprising:
providing a stack structure with at least one first sacrificial layer, at least two dielectric layers, and at least one second sacrificial layer; the second sacrificial layer is insulated from the first sacrificial layer by the dielectric layer;
etching the stack structure to form a receiving space; the receiving space comprises a first receiving portion, and several second receiving portions communicated with the first receiving portion; the first receiving portion crossed through the stack structure; each second receiving portion is coplanar with the corresponding first sacrificial layer;
forming a blocking layer and at least one floating gate layer;
removing a partial of the floating gate layer receiving in the first receiving portion, for making the floating gate layer being completely received in the second receiving portion;
forming a tunnel dielectric layer, a channel layer, and a filling layer in the first receiving portion in that order;
removing the first sacrificial layers and the second sacrificial layers;
forming a control gate at the positions of the removed first sacrificial layer, and erasing layers at the positions of the removed second sacrificial layers, to form the semiconductor,
wherein the second sacrificial layer is provided in a specified pattern comprising two parallel first portions along a second horizontal direction and at least two parallel second portions along a third direction, at least one end of the second portion is in contact with the first portion, and the first portion establishes an electrical connection between the erasing layer and an external circuit.

### Claim 2 (depends on 1)

The method of claim 1, wherein when the semiconductor executes the data erasing process, a positive voltage is applied on the erasing layer, the floating gate layer floats, a voltage less than the positive voltage is applied on the control gate layer; the electron passing path is from the floating gate layer to the erasing layer by passing through the overlapped portion of the dielectric layer between the erasing portion and the control gate layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein along a direction parallel with the control gate layer, the erasing layer is insulated from the channel layer by the dielectric layer and the blocking layer in the receiving space.

### Claim 4 (depends on 1)

The method of claim 1, wherein the erasing layer is in contact with the erasing layer in the adjacent storing cell in a whole shape technology.

### Claim 5 (depends on 1)

The method of claim 1, wherein along a direction perpendicular to the stack structure, the erasing layer is partly overlapped with the floating gate layer.