# US 12,004,343 B2 · Method of manufacturing capacitor connecting line of memory

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- Number: US 12,004,343 B2
- Document ID: US12004343B2
- Status: Granted
- Kind: B2
- Application number: 17/648,464
- Filed: 2022-01-20
- Published: 2022-05-12
- Granted: 2024-06-04
- Earliest claimed: 2020-11-05
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Yang Chen
- Web page: https://patentgrep.com/patent/US12004343B2

## CPC

- H10B 12/482: {Bit lines}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present disclosure provides a method of manufacturing a capacitor connecting line of a memory and a memory. The method of manufacturing includes: forming a bit line layer and a first dielectric layer on a substrate sequentially; patterning the bit line layer and the first dielectric layer, and forming bit line structures arranged at intervals along a first direction and dielectric structures on tops of the bit line structures; forming an insulating layer on the substrate with the bit line structures and the dielectric structures formed thereon, to completely cover the bit line structures and the dielectric structures; forming second isolation structures arranged at intervals between adjacent bit line structures; and forming conductive structures between first isolation structures and the second isolation structures, and forming storage node contact structures.

## Claims

### Claim 1

A method of manufacturing a capacitor connecting line of a memory, comprising:
forming a bit line layer and a first dielectric layer on a substrate sequentially;
patterning the bit line layer and the first dielectric layer, and forming bit line structures arranged at intervals along a first direction and dielectric structures on tops of the bit line structures, wherein a width of a top cross section of the dielectric structures is larger than a width of a cross section of the bit line structures;
forming an insulating layer on the substrate with the bit line structures and the dielectric structures formed thereon, to completely cover the bit line structures and the dielectric structures;
patterning the insulating layer with the dielectric structures as a mask in the first direction, forming first isolation structures on sidewalls of the bit line structures, and patterning the insulating layer in a second direction, to form second isolation structures arranged at intervals between adjacent bit line structures; and
forming conductive structures between the first isolation structures and the second isolation structures, and forming storage node contact structures.

### Claim 2 (depends on 1)

The method of manufacturing a capacitor connecting line of a memory according to claim 1, after the forming an insulating layer on the substrate with the bit line structures and the dielectric structures formed thereon, the method further comprises:
forming an oxide mask layer on the insulating layer; and
patterning the oxide mask layer, to form a same pattern as the dielectric structures in the insulating layer, wherein the insulating layer comprises a silicon nitride layer, an isolation layer and a silicon nitride insulating layer stacked sequentially.

### Claim 3 (depends on 2)

The method of manufacturing a capacitor connecting line of a memory according to claim 2, after the forming an oxide mask layer on the insulating layer, the method further comprises:
forming a carbon mask layer and a second dielectric layer sequentially on a surface of the insulating layer through a deposition process, and the second dielectric layer comprising a silicon nitride layer and/or a silicon oxynitride layer.

### Claim 4 (depends on 3)

The method of manufacturing a capacitor connecting line of a memory according to claim 3, before the patterning the insulating layer with the dielectric structures as a mask in the first direction, forming first isolation structures on sidewalls of the bit line structures, and patterning the insulating layer in a second direction, to form second isolation structures arranged at intervals between adjacent bit line structures, the method comprises:
forming a photolithography coating on the second dielectric layer, and the photolithography coating comprising a photolithography anti-reflective layer and a photoresist layer;
performing photolithography treatment on the photolithography coating, to obtain a photolithography material sacrificial layer patterned;
forming an oxide layer on the photolithography material sacrificial layer and the second dielectric layer through a deposition process;
etching the oxide layer through a dry etching process, to obtain the photolithography anti-reflective layer and a side wall of the photolithography anti-reflective layer; and
removing the photolithography anti-reflective layer through an oxide gas, to obtain oxide sidewalls on the bit line structures.

### Claim 5 (depends on 4)

The method of manufacturing a capacitor connecting line of a memory according to claim 4, wherein the forming conductive structures between the first isolation structures and the second isolation structures, and forming storage node contact structures comprises:
etching the second dielectric layer and the carbon mask layer with the oxide sidewalls as a mask and removing the oxide sidewalls, to obtain a patterned carbon mask layer; and
performing dry etching on the insulating layer with the patterned carbon mask layer and the dielectric structures as a mask, until the substrate is exposed, to form the first isolation structures in the first direction and the second isolation structures in the second direction.

### Claim 6 (depends on 5)

The method of manufacturing a capacitor connecting line of a memory according to claim 5, wherein the forming conductive structures between the first isolation structures and the second isolation structures, and forming storage node contact structures further comprises:
removing the carbon mask layer through a dry etching process; and
removing the oxide mask layer through a dry etching process, and forming the conductive structures between the first isolation structures and the second isolation structures, to form the storage node contact structures.

### Claim 7 (depends on 5)

The method of manufacturing a capacitor connecting line of a memory according to claim 5, wherein
a film thickness of the insulating layer is 80 nm to 120 nm, and/or a film thickness of the carbon mask layer is 80 nm to 130 nm, and a film thickness of the second dielectric layer is 25 nm to 45 nm.

### Claim 8 (depends on 2)

The method of manufacturing a capacitor connecting line of a memory according to claim 2, wherein
an etching ratio of the oxide mask layer and the insulating layer by dry etching ranges from 1:7 to 1:15.

### Claim 9 (depends on 8)

The method of manufacturing a capacitor connecting line of a memory according to claim 8,
when the oxide mask layer is removed through a dry etching process, an etching ratio of the oxide mask layer and the insulating layer is greater than or equal to 1:1.