# US 12,004,342 B2 · Method for manufacturing semiconductor structure and semiconductor structure

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- Number: US 12,004,342 B2
- Document ID: US12004342B2
- Status: Granted
- Kind: B2
- Application number: 17/502,247
- Filed: 2021-10-15
- Published: 2022-08-11
- Granted: 2024-06-04
- Earliest claimed: 2021-02-09
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Jingwen Lu; Hai-Han Hung
- Web page: https://patentgrep.com/patent/US12004342B2

## CPC

- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/482: {Bit lines}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, and forming bit lines extending in a first direction and trenches between the adjacent bit lines on the substrate; forming a dielectric layer and a contact layer filling the trenches, parts of the dielectric layer and parts of the contact layer being arranged at intervals in the first direction, both the dielectric layer and the contact layer being in contact with the substrate, and the contact layer having first gaps; removing part of the contact layer, to expose the first gaps; forming a filling layer to fill the first gaps; and etching the contact layer and the filling layer back.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising:
providing a substrate, and forming bit lines extending in a first direction and trenches located between adjacent bit lines of the bit lines on the substrate;
forming a dielectric layer and a contact layer filling the trenches, parts of the dielectric layer and parts of the contact layer being arranged at intervals in the first direction, both the dielectric layer and the contact layer being in contact with the substrate, and the contact layer having first gaps;
removing a second part of the contact layer, to expose the first gaps;
forming a filling layer to fill the first gaps; and
etching the contact layer and the filling layer back.

### Claim 2 (depends on 1)

The method for manufacturing a semiconductor structure of claim 1, wherein the forming a contact layer comprises: forming an initial contact layer filling the trenches; and patterning the initial contact layer, to form a plurality of discrete parts of the contact layer and spacer grooves between adjacent parts of the contact layer in the trenches.

### Claim 3 (depends on 2)

The method for manufacturing a semiconductor structure of claim 2, wherein a method for forming the initial contact layer comprises: low-pressure chemical vapor deposition; wherein process parameters of the low-pressure chemical vapor deposition comprise: a temperature of 380° C. to 500° C. and an air pressure of 1 Torr to 3 Torr.

### Claim 4 (depends on 2)

The method for manufacturing a semiconductor structure of claim 2, wherein the patterning the initial contact layer comprises: forming a mask layer extending in a second direction on the initial contact layer; and performing dry etching on the initial contact layer by using the mask layer as a mask, to form the spacer grooves, until bottoms of the spacer grooves expose the substrate, wherein the second direction is different from the first direction.

### Claim 5 (depends on 4)

The method for manufacturing a semiconductor structure of claim 4, wherein an angle between the second direction and the first direction is 75° to 90°.

### Claim 6 (depends on 2)

The method for manufacturing a semiconductor structure of claim 2, wherein the forming a dielectric layer comprises: forming the dielectric layer to fill the spacer grooves, the dielectric layer having second gaps.

### Claim 7 (depends on 6)

The method for manufacturing a semiconductor structure of claim 6, further comprising: while removing the second part of the contact layer, to expose the first gaps, removing a second part of the dielectric layer, to expose the second gaps.

### Claim 8 (depends on 6)

The method for manufacturing a semiconductor structure of claim 6, wherein while the filling layer is formed to fill the first gaps, the filling layer also fills the second gaps.

### Claim 9 (depends on 6)

The method for manufacturing a semiconductor structure of claim 6, wherein the forming a dielectric layer comprises: forming a first sub-dielectric layer, the first sub-dielectric layer covering bottoms and side walls of the spacer grooves; and forming a second sub-dielectric layer, the second sub-dielectric layer being located on a surface of the first sub-dielectric layer and filling the spacer grooves, material of the second sub-dielectric layer being different from material of the first sub-dielectric layer, and the second sub-dielectric layer having the second gaps.

### Claim 10 (depends on 9)

The method for manufacturing a semiconductor structure of claim 9, wherein in the first direction, a ratio of thickness of the first sub-dielectric layer to width of the spacer grooves is 1:4 to 1:3.

### Claim 11 (depends on 10)

The method for manufacturing a semiconductor structure of claim 10, wherein a ratio of thickness of the second sub-dielectric layer to the thickness of the first sub-dielectric layer is 3:1 to 2:1.

### Claim 12 (depends on 9)

The method for manufacturing a semiconductor structure of claim 9, wherein before the second part of the contact layer is removed, the first sub-dielectric layer and the second sub-dielectric layer on a top surface of the contact layer are also removed.

### Claim 13 (depends on 1)

The method for manufacturing a semiconductor structure of claim 1, after etching the contact layer and the filling layer back, further comprising: forming a conductive layer on a remaining part of the contact layer and a remaining part of the filling layer.

### Claim 14

A semiconductor structure, comprising:
a substrate, the substrate having bit lines extending in a first direction;
a dielectric layer and a contact layer located between adjacent bit lines of the bit lines, parts of the dielectric layer and parts of the contact layer being arranged at intervals in the first direction, and both the dielectric layer and the contact layer being in contact with the substrate; and
a filling layer located in the contact layer, and the contact layer exposing a top surface of the filling layer;
wherein the semiconductor structure is manufactured by a method comprising:
providing the substrate, and forming the bit lines extending in the first direction and trenches located between the adjacent bit lines on the substrate;
forming the dielectric layer and the contact layer filling the trenches, the parts of the dielectric layer and the parts of the contact layer being arranged at the intervals in the first direction, both the dielectric layer and the contact layer being in contact with the substrate, and the contact layer having first gaps;
removing a second part of the contact layer, to expose the first gaps;
forming the filling layer to fill the first gaps; and
etching the contact layer and the filling layer back.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14, wherein the filling layer is also located in the dielectric layer, and the dielectric layer exposes the top surface of the filling layer.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, wherein the dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer;
the first sub-dielectric layer covers a surface of the substrate and side walls of the contact layer;
the second sub-dielectric layer is located on a surface of the first sub-dielectric layer; material of the second sub-dielectric layer is different from material of the first sub-dielectric layer, the filling layer is also located in the second sub-dielectric layer, and the second sub-dielectric layer exposes the top surface of the filling layer.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, wherein the material of the first sub-dielectric layer comprises silicon nitride; the material of the second sub-dielectric layer comprises silicon oxide; and material of the filling layer comprises silicon nitride.

### Claim 18 (depends on 14)

The semiconductor structure of claim 14, wherein the contact layer is a capacitor contact layer.

### Claim 19 (depends on 14)

The semiconductor structure of claim 14, wherein material of the contact layer comprises polysilicon.