# US 12,004,340 B2 · Semiconductor memory device and method for forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,004,340 B2 - Document ID: US12004340B2 - Status: Granted - Kind: B2 - Application number: 17/688,858 - Filed: 2022-03-07 - Published: 2023-06-01 - Granted: 2024-06-04 - Earliest claimed: 2021-12-01 - Assignees: Fujian Jinhua Integrated Circuit Co., Ltd. - Applicants: Fujian Jinhua Integrated Circuit Co., Ltd. - Inventors: Yifei Yan - Web page: https://patentgrep.com/patent/US12004340B2 ## CPC - H10B 12/315: {with the capacitor higher than a bit line} - H10D 1/042: {using deposition processes to form electrode extensions} - H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug} - H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)} - H10B 12/482: {Bit lines} - H10B 12/485: {Bit line contacts} - H10D 1/716: {having vertical extensions} - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor memory device including a substrate, bit lines, contacts, a dielectric layer, storage node pads and a capacitor structure. The bit lines are disposed on the substrate and include a plurality of first bit lines and at least one second bit line. The contacts are disposed on the substrate and alternately and separately disposed with the bit lines. The dielectric layer is disposed over the contacts and bit lines. The storage node pads are disposed in the dielectric layer and respectively contact the contacts. The capacitor structure is disposed on the storage node pads and includes a plurality of first capacitors and at least one second capacitor located above at least one second bit line. Therefore, the semiconductor memory device can achieve more optimized device performance. ## Claims ### Claim 1 A semiconductor memory device, comprising: a substrate, having a cell region and a periphery region; a plurality of bit lines, disposed on the substrate, wherein the bit lines comprise a plurality of first bit lines within the cell region and at least one second bit line within the periphery region, the at least one second bit line being disposed outside all of the first bit lines, wherein the at least one second bit line is a dummy bit line; a plurality of contacts, disposed on the substrate, and alternatively and separately disposed with the bit lines; a dielectric layer, disposed over the contacts and the bit lines; a plurality of storage node pads, disposed in the dielectric layer and respectively connected to the contacts; and a capacitor structure, disposed on the storage node pads, the capacitor structure comprises a plurality of first capacitors and at least one second capacitor, the plurality of first capacitors being respectively aligned with the storage node pads, and the at least one second capacitor being located over the at least one second bit line. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, wherein a bottom surface of the at least one second capacitor is in direct contact with the dielectric layer. ### Claim 3 (depends on 1) The semiconductor memory device of claim 1, wherein the at least one second capacitor is located over a portion of one of the contacts and a portion of the at least one second bit line simultaneously. ### Claim 4 (depends on 1) The semiconductor memory device of claim 1, wherein each of the bit lines comprises a semiconductor layer, a barrier layer, a conductive layer and a cap layer sequentially stacked from bottom to top, and the at least one second capacitor is in direct contact with the cap layer of the at least one second bit line. ### Claim 5 (depends on 4) The semiconductor memory device of claim 4, wherein the at least one second capacitor is extended into the cap layer of the at least one second bit line. ### Claim 6 (depends on 1) The semiconductor memory device of claim 1, wherein a bottom surface of the at least one second capacitor is lower than a top surface of the at least one second bit line. ### Claim 7 (depends on 1) The semiconductor memory device of claim 1, wherein a width of the at least one second bit line is larger than a width of the first bit lines. ### Claim 8 (depends on 1) The semiconductor memory device of claim 1, wherein the capacitor structure further comprises at least one third capacitor respectively located corresponding to the contacts, and the third capacitors are in direct contact with the dielectric layer. ### Claim 9 (depends on 8) The semiconductor memory device of claim 8, wherein the at least one third capacitor is disposed outside all of the first capacitors, and the at least one third capacitor is disposed between the first capacitors and the at least one second capacitor. ### Claim 10 (depends on 8) The semiconductor memory device of claim 8, wherein a bottom surface of the at least one third capacitor is lower than a top surface of the dielectric layer. ### Claim 11 A semiconductor memory device, comprising: a substrate; a plurality of bit lines, disposed on the substrate, wherein the bit lines comprise a plurality of first bit lines and at least one second bit line, the at least one second bit line being disposed outside all of the first bit lines; a plurality of contacts, disposed on the substrate, and alternatively and separately disposed with the bit lines; a dielectric layer, disposed over the contacts and the bit lines; a plurality of storage node pads, disposed in the dielectric layer and respectively connected to the contacts; and a capacitor structure, disposed on the storage node pads, the capacitor structure comprises a plurality of first capacitors and at least one second capacitor, the plurality of first capacitors being respectively aligned with the storage node pads, and the at least one second capacitor being located over the at least one second bit line, wherein the at least one second capacitor is isolated from any one of the contacts. ### Claim 12 (depends on 11) The semiconductor memory device of claim 11, wherein a bottom surface of the at least one second capacitor is in direct contact with the dielectric layer. ### Claim 13 (depends on 11) The semiconductor memory device of claim 11, wherein the at least one second capacitor is located over a portion of one of the contacts and a portion of the at least one second bit line simultaneously. ### Claim 14 (depends on 11) The semiconductor memory device of claim 11, wherein each of the bit lines comprises a semiconductor layer, a barrier layer, a conductive layer and a cap layer sequentially stacked from bottom to top, and the at least one second capacitor is in direct contact with the cap layer of the at least one second bit line. ### Claim 15 (depends on 14) The semiconductor memory device of claim 14, wherein the at least one second capacitor is extended into the cap layer of the at least one second bit line. ### Claim 16 (depends on 11) The semiconductor memory device of claim 11, wherein a bottom surface of the at least one second capacitor is lower than a top surface of the at least one second bit line. ### Claim 17 (depends on 11) The semiconductor memory device of claim 11, wherein a width of the at least one second bit line is larger than a width of the first bit lines. ### Claim 18 (depends on 11) The semiconductor memory device of claim 11, wherein the capacitor structure further comprises at least one third capacitor respectively located corresponding to the contacts, and the third capacitors are in direct contact with the dielectric layer. ### Claim 19 (depends on 18) The semiconductor memory device of claim 18, wherein the at least one third capacitor is disposed outside all of the first capacitors, and the at least one third capacitor is disposed between the first capacitors and the at least one second capacitor. ### Claim 20 A semiconductor memory device, comprising: a substrate; a plurality of bit lines, disposed on the substrate, wherein the bit lines comprise a plurality of first bit lines and at least one second bit line, the at least one second bit line being disposed outside all of the first bit lines; a plurality of contacts, disposed on the substrate, and alternatively and separately disposed with the bit lines; a dielectric layer, disposed over the contacts and the bit lines; a plurality of storage node pads, disposed in the dielectric layer and respectively connected to the contacts; and a capacitor structure, disposed on the storage node pads, the capacitor structure comprises a plurality of first capacitors and at least one second capacitor, the plurality of first capacitors being respectively aligned with the storage node pads, and the at least one second capacitor being located over the at least one second bit line, wherein each of the bit lines comprises a semiconductor layer, a barrier layer, a conductive layer and a cap layer sequentially stacked from bottom to top, and the at least one second capacitor is in direct contact with the cap layer of the at least one second bit line.