# US 12,004,292 B2 · Printed circuit board > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,004,292 B2 - Document ID: US12004292B2 - Status: Granted - Kind: B2 - Application number: 17/706,920 - Filed: 2022-03-29 - Published: 2023-05-11 - Granted: 2024-06-04 - Earliest claimed: 2021-11-09 - Assignees: Samsung Electro-Mechanics Co., Ltd. - Applicants: Samsung Electro-Mechanics Co., Ltd. - Inventors: Man Gon Kim - Web page: https://patentgrep.com/patent/US12004292B2 ## CPC - H05K 1/0298: {Multilayer circuits} - H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)} - H05K 1/144: {Stacked arrangements of planar printed circuit boards} - H05K 3/0097: {Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards (H05K3/0052 takes precedence)} - H05K 3/4623: {the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards (H05K3/462 takes precedence)} - H05K 1/112: {directly combined with via connections} - H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)} - H05K 2201/096: Vertically aligned vias, holes or stacked vias - H05K 2203/061: of previously made multilayered subassemblies - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A printed circuit board includes: a first multilayer substrate including first and second vias adjacent to each other in a stacking direction of the printed circuit board; a second multilayer substrate disposed on the first multilayer substrate in the stacking direction and including third and fourth vias adjacent to each other in the stacking direction; and an adhesive layer connecting respective one surfaces of the first and second multilayer substrates to each other. Each of the first to fourth vias has one surface and the other surface facing the one surface, the one surface being closer to the adhesive layer than the other surface, and the one surface having a larger transverse cross-sectional area than the other surface. ## Claims ### Claim 1 A printed circuit board comprising: a first multilayer substrate including first and second vias adjacent to each other in a stacking direction of the printed circuit board; a second multilayer substrate disposed on the first multilayer substrate in the stacking direction and including third and fourth vias adjacent to each other in the stacking direction; an insulating layer arranged between the first and second multilayer substrates; and an adhesive layer connecting respective one surfaces of the first and second multilayer substrates to each other, wherein each of the first to fourth vias has a first surface and a second surface facing the first surface, the first surface being closer to the adhesive layer than the second surface, and the first surface having a larger transverse cross-sectional area than the second surface, wherein the adhesive layer is disposed between a circuit pattern of the first multilayer substrate and a circuit pattern of the second multilayer substrate to connect the circuit pattern of the first multilayer substrate and the circuit pattern of the second multilayer substrate to each other, wherein the adhesive layer has a side surface which is substantially coplanar with a side surface of at least one of the circuit pattern of the first multilayer substrate or the circuit pattern of the second multilayer substrate, wherein the circuit pattern of the first multilayer substrate and the circuit pattern of the second multilayer substrate are embedded in the insulating layer, and wherein the second multilayer substrate includes a core substrate having upper and lower surfaces such that more build-up layers are disposed between the insulating layer and the upper surface in the stacking direction than that disposed on the lower surface. ### Claim 2 (depends on 1) The printed circuit board of claim 1, wherein the adhesive layer includes a conductive material. ### Claim 3 (depends on 1) The printed circuit board of claim 1, wherein each of all the vias in each of the first and second multilayer substrates has a largest transverse cross-sectional area in a region closest to the adhesive layer. ### Claim 4 (depends on 1) The printed circuit board of claim 1, wherein each of the first and second multilayer substrates further includes at least one build-up insulating layer, and the build-up insulating layer of each of the first and second multilayer substrates includes a different composition from the core substrate of the second multilayer substrate. ### Claim 5 (depends on 1) The printed circuit board of claim 1, wherein the second multilayer substrate further includes a through hole penetrating through the core substrate. ### Claim 6 (depends on 1) The printed circuit board of claim 1, further comprising: first and second insulating layers disposed on the first and second multilayer substrates, respectively; and first and second solder resist layers disposed on the first and second insulating layers, respectively. ### Claim 7 (depends on 6) The printed circuit board of claim 6, wherein each of the first and second insulating layers is a single-layered insulating layer. ### Claim 8 (depends on 6) The printed circuit board of claim 6, further comprising fifth and sixth vias penetrating through the first and second insulating layers, respectively, wherein each of the fifth and sixth vias has a transverse cross-sectional area that becomes smaller in a direction toward the adhesive layer. ### Claim 9 (depends on 1) The printed circuit board of claim 1, wherein each of the first and second via of the first multilayer substrate is symmetrical to each of the third and fourth vias of the second multilayer substrate. ### Claim 10 (depends on 1) The printed circuit board of claim 1, wherein a thickness of the adhesive layer is greater than a thickness of at least one of the circuit pattern of the first multilayer substrate or the circuit pattern of the second multilayer substrate.