# US 12,004,288 B2 · Resonant-coupled transmission line > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,004,288 B2 - Document ID: US12004288B2 - Status: Granted - Kind: B2 - Application number: 17/184,793 - Filed: 2021-02-25 - Published: 2022-08-25 - Granted: 2024-06-04 - Earliest claimed: 2021-02-25 - Assignees: Teradyne, Inc. - Applicants: Teradyne, Inc. - Inventors: Andrew Westwood - Web page: https://patentgrep.com/patent/US12004288B2 ## CPC - H01P 5/028: {between strip lines} - H05K 1/0222: {for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence} - G01R 1/0433: {Sockets for IC's or transistors} - G01R 1/0466: {concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding} - G01R 1/0483: {Sockets for unleaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips} - G01R 31/2886: {Features relating to contacting the IC under test, e.g. probe heads; chucks (G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06)} - G01R 31/2889: {Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence)} - H01P 3/003: {Coplanar lines} - H01P 3/08: Microstrips; Strip lines - H05K 1/0251: {related to vias or transitions between vias and transmission lines} - H05K 1/0219: {Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors} - H05K 1/0248: {Skew reduction or using delay lines} - H05K 2201/09254: Branched layout - H05K 2201/093: Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein - H05K 2201/09309: Core having two or more power planes; Capacitive laminate of two power planes - H05K 2201/09609: Via grid, i.e. two-dimensional array of vias or holes in a single plane - H05K 2201/09618: Via fence, i.e. one-dimensional array of vias - H05K 2201/09672: Superposed layout, i.e. in different planes - H05K 2201/09754: Connector integrally incorporated in the printed circuit board [PCB] or in housing - H05K 2201/09809: Coaxial layout - H01P: WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE (operating at optical frequencies G02B) - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract An example printed circuit board (PCB) includes a substrate having layers of a dielectric material, where the layers of dielectric material include a first layer and a second layer; a conductive trace that is between the first layer and the second layer and that is parallel to the first layer and the second layer along at least part of a length of the conductive trace; and a conductive via that extends at least part-way through the layers of dielectric material and that connects electrically to the conductive trace, where the conductive via is configured also to connect electrically to a signal input to receive or to transmit a signal that has a center frequency span. ## Claims ### Claim 1 A printed circuit board (PCB) comprising: a substrate comprised of layers of dielectric material, the layers of dielectric material comprising a first layer and a second layer; a conductive trace that is between the first layer and the second layer and that is parallel to the first layer and the second layer along at least part of a length of the conductive trace; a conductive via that extends at least part-way through the layers of dielectric material and that connects electrically to the conductive trace, the conductive via being configured also to connect electrically to a signal input to receive a signal that has a center frequency span; a first ground layer that connects electrically to the conductive via, the first ground layer connecting to a reference ground voltage, the first ground layer being adjacent to the second layer, and the first ground layer being located a distance from the conductive trace that is substantially equal to one quarter (¼) of a wavelength of the center frequency span of the signal; and a second ground layer adjacent to the first ground layer and also connecting to the reference ground voltage, the conductive trace being between the first ground layer and the second ground layer. ### Claim 2 (depends on 1) The PCB of claim 1, wherein the conductive trace, the conductive via, the first ground layer, and the second ground layer form a first transmission line; and wherein the first transmission line is interleaved with other transmission lines on different layers of the PCB. ### Claim 3 (depends on 1) The PCB of claim 1, wherein the conductive trace, the conductive via, the first ground layer, and the second ground layer form a first transmission line; and wherein the first transmission is in a same layer of the substrate as one or more other transmission lines in the PCB. ### Claim 4 (depends on 1) The PCB of claim 1, further comprising; conductive traces that are between respective layers of dielectric material in the substrate and that are at least partly parallel to respective layers of dielectric material; conductive vias that extend at least part-way through the layers of dielectric material and that connect electrically to respective conductive traces, the conductive vias being configured also to connect electrically to respective signal inputs to receive respective signals that have center frequency spans; and third ground layers that connect electrically to respective ones of the conductive vias, each third ground layer connecting to the reference ground voltage, each third ground layer being located a distance from a respective conductive trace that is substantially equal to one quarter (¼) of a wavelength of a center frequency span of a signal received at a respective signal input. ### Claim 5 (depends on 4) The PCB of claim 4, wherein the first ground layer, the second ground layer, and the third ground layers are unbroken. ### Claim 6 (depends on 4) The PCB of claim 4, wherein the first ground layer, the second ground layer, and the third ground layers are electrically connected to a common reference ground voltage. ### Claim 7 (depends on 1) The PCB of claim 1, wherein a structure having a configuration of the conductive trace, the conductive via, the first ground layer, and the second ground layer is repeated in the substrate along a same dimension of the PCB. ### Claim 8 (depends on 7) The PCB of claim 7, wherein the same dimension is horizontal. ### Claim 9 (depends on 1) The PCB of claim 1, wherein structures having a configuration of the conductive trace, the conductive via, the first ground layer, and the second ground layer are stacked in the substrate along a dimension orthogonal to the layers of dielectric material. ### Claim 10 (depends on 1) The PCB of claim 1, wherein the signal input comprises an input transmission line. ### Claim 11 (depends on 1) The PCB of claim 1, wherein the signal input comprises or a coaxial connector configured to connect directly to the conductive via. ### Claim 12 (depends on 1) The PCB of claim 1, wherein the signal input is also configured to source signals for output from the PCB. ### Claim 13 (depends on 1) The PCB of claim 1, wherein the PCB comprise a device interface board (DIB) configured to hold devices under test (DUTs) for testing; and wherein the signal input electrically connects to a signal path between the DIB and a test instrument configured to generate the signal or to receive the signal. ### Claim 14 (depends on 1) The PCB of claim 1, wherein the first layer is comprised of one or more dielectric layers and the second layer is comprised of one or more dielectric layers; wherein the first layer and the second layer are asymmetric in that the first layer and the second layer have different thicknesses; and wherein a thickness of the second layer is substantially equal to one quarter (¼) of a wavelength of the center frequency span of the signal. ### Claim 15 (depends on 1) The PCB of claim 1, further comprising: ground vias that are conductive and that encircle the conductive via partly, the ground vias connecting electrically to the first ground layer. ### Claim 16 (depends on 15) The PCB of claim 15, wherein ground vias are absent at a point of electrical connection between the conductive trace and the conductive via. ### Claim 17 (depends on 1) The PCB of claim 1, further comprising: a conductor configured to create an electrical connection between the conductive trace and the conductive via, the conductor to match an impedance of the conductive trace to an impedance of the conductive via. ### Claim 18 (depends on 17) The PCB of claim 17, wherein the conductor is between the first layer and the second layer and is parallel to the first layer and the second layer along at least part of a length of the conductor. ### Claim 19 (depends on 18) The PCB of claim 18, wherein the conductive trace comprises a stripline conductor; and wherein the conductor has a width that differs from a width of the conductive trace. ### Claim 20 (depends on 1) The PCB of claim 1, further comprising: ground vias that are conductive and that run substantially parallel to the conductive trace along at least part of a length of the conductive trace, the ground vias connecting electrically to the first ground layer. ### Claim 21 (depends on 1) The PCB of claim 1, wherein the first ground layer reflects at least the center frequency span of the signal along the conductive via and a resulting reflected signal launches into the conductive trace. ### Claim 22 (depends on 1) The PCB of claim 1, wherein the signal comprises a radio frequency signal. ### Claim 23 (depends on 1) The PCB of claim 1, wherein the signal comprises a microwave signal. ### Claim 24 (depends on 1) The PCB of claim 1, wherein the signal comprises a millimeter wave signal. ### Claim 25 (depends on 1) The PCB of claim 1, wherein the first layer and the second layer comprise different dielectrics. ### Claim 26 (depends on 25) The PCB of claim 25, wherein the different dielectrics have at least one of different dispersion characteristics or different insertion losses. ### Claim 27 (depends on 25) The PCB of claim 25, wherein the different dielectrics have different chemical properties such that, from a perspective of the signal, the first layer and the second layer have a same electromagnetic thickness even though the first and second layers have different physical thicknesses. ### Claim 28 (depends on 1) The PCB of claim 1, wherein the signal comprises a sinusoidal signal. ### Claim 29 (depends on 1) The PCB of claim 1, wherein the signal comprises a modulated signal. ### Claim 30 (depends on 1) The PCB of claim 1, wherein the signal is one of multiple signals that move bidirectionally through the conductive trace. ### Claim 31 (depends on 30) The PCB of claim 30, wherein the multiple signals comprise two signals that are separated by a difference of frequency and that share a common overall bandwidth. ### Claim 32 A system comprising: a device interface board (DIB) configured to hold devices under test (DUTs) for testing; a test instrument configured to output signals to test the DUTs, the DIB for routing the signals to the DUTS; and a control system comprising at least one processing device configured to control operation of the test instrument to output the signals to test the DUTs; wherein the DIB comprises: a substrate comprised of layers of dielectric material, the layers of dielectric material comprising a first layer and a second layer; a conductive trace that is between the first layer and the second layer and that is parallel to the first layer and the second layer along at least part of a length of the conductive trace; a conductive via that extends at least part-way through the layers of dielectric material and that connects electrically to the conductive trace, the conductive via being configured also to connect electrically to a signal input to receive a signal that has a center frequency span; a first ground layer that connects electrically to the conductive via, the first ground layer connecting to a reference ground voltage, the first ground layer being adjacent to the second layer, and the first ground layer being located a distance from the conductive trace that is substantially equal to one quarter (¼) of a wavelength of the center frequency span of the signal; and a second ground layer adjacent to the first ground layer and connecting to the reference ground voltage, the conductive trace being between the first ground layer and the second ground layer. ### Claim 33 (depends on 32) The system of claim 32, wherein the first layer is comprised of one or more dielectric layers and the second layer is comprised of one or more dielectric layers; wherein the first layer and the second layer are asymmetric in that the first layer and the second layer have different thicknesses; and wherein a thickness of the second layer is substantially equal to one quarter (¼) of a wavelength of the center frequency span of the signal. ### Claim 34 (depends on 32) The system of claim 32, wherein the DIB further comprises: ground vias that are conductive and that encircle the conductive via partly, the ground vias connecting electrically to the first ground layer. ### Claim 35 (depends on 32) The system of claim 32, wherein the DIB further comprises: a conductor configured to create an electrical connection between the conductive trace and the conductive via, the conductor to match an impedance of the conductive trace to an impedance of the conductive via. ### Claim 36 (depends on 32) The system of claim 32, wherein a structure having a configuration of the conductive trace, the conductive via, the first ground layer, and the second ground layer is repeated in the substrate. ### Claim 37 (depends on 32) The system of claim 32, wherein structures having a configuration of the conductive trace, the conductive via, the first ground layer, and the second ground layer are stacked in the substrate along a dimension orthogonal to the layers of dielectric material. ### Claim 38 A device interface board (DIB) configured to act as a mechanical and electrical interface between a device under test (DUT) and a test instrument of a test system, the DIB comprising: a substrate comprised of layers of dielectric material, the layers of dielectric material comprising a first layer and a second layer; a conductive trace that is between the first layer and the second layer and that is parallel to the first layer and the second layer along at least part of a length of the conductive trace; a conductive via that extends through the layers of dielectric material and that connects electrically to the conductive trace, the conductive via being configured also to connect electrically to a signal input to receive a signal having a center frequency span; a ground layer to cause the signal to reflect along the conductive via, the ground layer also to inhibit dissipation of at least part of the signal into the substrate; and a conductor to create an electrical connection between the conductive trace and the conductive via, the conductor to match an impedance of the conductive trace to the conductive via to inhibit signal reflection along the conductive trace.