# US 12,003,879 B2 · Pixel unit and signal processing method for pixel unit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,003,879 B2 - Document ID: US12003879B2 - Status: Granted - Kind: B2 - Application number: 17/610,002 - Filed: 2021-06-25 - Published: 2022-11-03 - Granted: 2024-06-04 - Earliest claimed: 2020-11-06 - Assignees: Peking University - Applicants: Peking University - Inventors: Xiaoyan Liu; Liqiao Liu; Gang Du - Web page: https://patentgrep.com/patent/US12003879B2 ## CPC - H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components - H04N 25/00: Circuitry of solid-state image sensors [SSIS]; Control thereof - H04N 25/708: Pixels for edge detection - H04N 25/709: Circuitry for control of the power supply - H04N 25/79: Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors - H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes} - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract The present application discloses a pixel unit and a signal processing method for a pixel unit. The pixel unit includes at least one pixel, and the pixel includes: an N-type main pixel, a P-type main pixel, and a sub-pixel; and the sub-pixel is located between the N-type main pixel and the P-type main pixel; or the pixel includes at least a first pixel and a second pixel that are adjacent to each other; the first pixel includes an N-type main pixel, and the second pixel includes a P-type main pixel; the first pixel and the second pixel share one sub-pixel; the sub-pixel is configured to generate and output a signal difference between the N-type main pixel and the P-type main pixel according to the current. By adding a sub-pixel between two main pixels, the sub-pixel generates and outputs the signal difference between the N-type main pixel and the P-type main pixel according to the current sent by the two main pixels, so that the received signal can be efficiently processed directly to reduce the amount of output data. Since there is no need to increase a circuit, the pixel area will not increase due to a complicated circuit. ## Claims ### Claim 1 A pixel unit comprising: at least one pixel comprising an N-type main pixel, a P-type main pixel, and a sub-pixel, wherein: both the N-type main pixel and the P-type main pixel are configured to output a current corresponding to an exposure intensity to the sub-pixel according to exposure; and the sub-pixel is located between the N-type main pixel and the P-type main pixel, and is configured to generate and output a signal difference between the N-type main pixel and the P-type main pixel according to the current, and wherein the N-type main pixel, the P-type main pixel and the sub-pixel all comprise an N-type MOS transistor structure, a buried oxide layer and a substrate. ### Claim 2 (depends on 1) The pixel unit according to claim 1, wherein the N-type MOS transistor structure comprises: an N-type MOS transistor source region, an N-type MOS transistor channel region, and an N-type MOS transistor drain region. ### Claim 3 (depends on 2) The pixel unit according to claim 2, wherein a thickness of a silicon film in the N-type MOS transistor channel region is 5 nanometers to 20 nanometers. ### Claim 4 (depends on 2) The pixel unit according to claim 2, wherein lengths of the N-type MOS transistor source region and the N-type MOS transistor drain region are 20 nanometers to 90 nanometers. ### Claim 5 (depends on 1) The pixel unit according to claim 1, wherein a thickness of the buried oxide layer is 10 nanometers to 30 nanometers. ### Claim 6 (depends on 1) The pixel unit according to claim 1, wherein the substrate in the N-type main pixel is an N-type doped well, and the substrate in the P-type main pixel is a P-type doped well. ### Claim 7 (depends on 1) The pixel unit according to claim 1, wherein shallow trench isolation is used for isolation between the N-type main pixel, the P-type main pixel and the sub-pixel. ### Claim 8 A pixel unit comprising: at least a first pixel and a second pixel that are adjacent to each other, the first pixel comprising an N-type main pixel, the second pixel comprising a P-type main pixel, and the first pixel and the second pixel sharing one sub-pixel, wherein: both the N-type main pixel and the P-type main pixel are configured to output a current corresponding to an exposure intensity to the sub-pixel according to exposure; and the sub-pixel is configured to generate and output a signal difference between the N-type main pixel and the P-type main pixel according to the current, and wherein the N-type main pixel, the P-type main pixel and the sub-pixel all comprise an N-type MOS transistor structure, a buried oxide layer and a substrate. ### Claim 9 (depends on 8) The pixel unit according to claim 8, wherein the N-type MOS transistor structure comprises: an N-type MOS transistor source region, an N-type MOS transistor channel region, and an N-type MOS transistor drain region. ### Claim 10 (depends on 9) The pixel unit according to claim 9, wherein a thickness of a silicon film in the N-type MOS transistor channel region is 5 nanometers to 20 nanometers. ### Claim 11 (depends on 9) The pixel unit according to claim 9, wherein lengths of the N-type MOS transistor source region and the N-type MOS transistor drain region are 20 nanometers to 90 nanometers. ### Claim 12 (depends on 8) The pixel unit according to claim 8, wherein a thickness of the buried oxide layer is 10 nanometers to 30 nanometers. ### Claim 13 (depends on 8) The pixel unit according to claim 8, wherein the substrate in the N-type main pixel is an N-type doped well, and the substrate in the P-type main pixel is a P-type doped well. ### Claim 14 (depends on 8) The pixel unit according to claim 8, wherein shallow trench isolation is used for isolation between the N-type main pixel, the P-type main pixel and the sub-pixel. ### Claim 15 (depends on 1) A signal processing method for a pixel unit, in which the pixel unit according to claim 1 is used, the method comprising the following steps: applying a positive voltage to the N-type main pixel in the pixel unit, and applying a negative voltage to the P-type main pixel; exposing the pixel unit; outputting, by the N-type main pixel and the P-type main pixel, a current corresponding to an exposure intensity to the sub-pixel according to the exposure; and generating and outputting, by the sub-pixel, a signal difference between the N-type main pixel and the P-type main pixel according to the current. ### Claim 16 (depends on 8) A signal processing method for a pixel unit, in which the pixel unit according to claim 8 is used, the method comprising the following steps: applying a positive voltage to the N-type main pixel in the pixel unit, and applying a negative voltage to the P-type main pixel; exposing the pixel unit; outputting, by the N-type main pixel and the P-type main pixel, a current corresponding to an exposure intensity to the sub-pixel according to the exposure; and generating and outputting, by the sub-pixel, a signal difference between the N-type main pixel and the P-type main pixel according to the current.