# US 12,003,870 B2 · Binning in hybrid pixel structure of image pixels and event vision sensor (EVS) pixels > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,003,870 B2 - Document ID: US12003870B2 - Status: Granted - Kind: B2 - Application number: 17/721,801 - Filed: 2022-04-15 - Published: 2023-10-19 - Granted: 2024-06-04 - Earliest claimed: 2022-04-15 - Assignees: Sony Semiconductor Solutions Corporation - Applicants: Sony Semiconductor Solutions Corporation - Inventors: Pooria Mostafalu; Frederick T. Brady; Sungin Han; Hongyi Mi - Web page: https://patentgrep.com/patent/US12003870B2 ## CPC - H04N 25/46: by combining or binning pixels - H04N 25/42: by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode - H04N 25/47: Image sensors with pixel address output; Event-driven image sensors; Selection of pixels to be read out based on image data - H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components - H10F 39/8023: {Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery} - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract Binning in a hybrid pixel structure of image pixels and event vision sensor (EVS) pixels. In one embodiment, the imaging sensor includes a pixel array including a plurality of pixel circuits and a plurality of binning transistors. A first portion of the plurality of pixel circuits individually includes an intensity photodiode. A second portion of the plurality of pixel circuits individually includes an event vision sensor (EVS) photodiode. The plurality of binning transistors is configured to bin together at least one of the first portion or the second portion. ## Claims ### Claim 1 An imaging sensor comprising: a pixel array including a plurality of pixel circuits; and a plurality of binning transistors, wherein a first portion of the plurality of pixel circuits individually includes two or more intensity photodiodes and a second portion of the plurality of pixel circuits individually includes two or more event vision sensor (EVS) photodiodes that are separate and distinct from the two or more intensity photodiodes, and wherein the plurality of binning transistors is configured to bin together the first portion, bin together the second portion, and bin together the first portion and bin together the second portion, respectively. ### Claim 2 (depends on 1) The imaging sensor according to claim 1, wherein the plurality of binning transistors includes a plurality of SNG transistors that horizontally bin together sense nodes of the second portion on a row-by-row basis of the pixel array. ### Claim 3 (depends on 1) The imaging sensor according to claim 1, wherein the plurality of binning transistors includes a plurality of VNG transistors that vertically bin together sense nodes of the second portion on a column-by-column basis of the pixel array. ### Claim 4 (depends on 1) The imaging sensor according to claim 1, wherein the plurality of binning transistors includes a plurality of ALSEN transistors that horizontally bin together floating diffusions of the first portion on a row-by-row basis of the pixel array. ### Claim 5 (depends on 1) The imaging sensor according to claim 1, wherein the plurality of binning transistors includes a plurality of FDI transistors that vertically bin together floating diffusions of the first portion on a column-by-column basis of the pixel array. ### Claim 6 (depends on 1) The imaging sensor according to claim 1, wherein the plurality of pixel circuits forms a hybrid unit pixel, wherein the first portion with respect to the hybrid unit pixel is twelve intensity photodiodes, wherein the second portion with respect to the hybrid unit pixel is four EVS photodiodes, and wherein each of the twelve intensity photodiodes has a gate that shares one of four floating diffusions. ### Claim 7 (depends on 1) The imaging sensor according to claim 1, wherein the plurality of pixel circuits forms a hybrid unit pixel, wherein the first portion with respect to the hybrid unit pixel is fourteen intensity photodiodes, wherein the second portion with respect to the hybrid unit pixel is four EVS photodiodes, and wherein each of the fourteen intensity photodiodes has a gate that shares one of four floating diffusions. ### Claim 8 (depends on 7) The imaging sensor according to claim 7, wherein the fourteen intensity photodiodes includes four intensity photodiodes with a blue light filter, six intensity photodiodes with a green light filter, and four intensity photodiodes with a red light filter. ### Claim 9 A method comprising: controlling, with control circuitry, a plurality of binning transistors according to a first mode; and controlling, with the control circuitry, the plurality of binning transistors to change from the first mode to a second mode, wherein, in the second mode, the plurality of binning transistors bins together a first portion of a plurality of pixel circuits in a pixel array and bins together a second portion of the plurality of pixel circuits, respectively, and wherein the first portion of the plurality of pixel circuits individually includes two or more intensity photodiodes and the second portion of the plurality of pixel circuits individually includes two or more vision sensor (EVS) photodiodes that are separate and distinct from the two or more intensity photodiodes. ### Claim 10 (depends on 9) The method according to claim 9, wherein the first mode is a non-binning mode, and wherein, in the non-binning mode, the plurality of binning transistors are in an OFF state. ### Claim 11 (depends on 9) The method according to claim 9, wherein the second mode is a first binning mode and the plurality of binning transistors includes a plurality of SNG transistors, and wherein, in the first binning mode, the control circuitry controls the plurality of SNG transistors to horizontally bin together sense nodes of the second portion on a row-by-row basis of the pixel array. ### Claim 12 (depends on 9) The method according to claim 9, wherein the second mode is a first binning mode and the plurality of binning transistors includes a plurality of VNG transistors, wherein, in the first binning mode, the control circuitry controls the plurality of VNG transistors to vertically bin together sense nodes of the second portion on a column-by-column basis of the pixel array. ### Claim 13 (depends on 9) The method according to claim 9, wherein the second mode is a first binning mode and the plurality of binning transistors includes a plurality of ALSEN transistors, and wherein, in the first binning mode, the control circuitry controls the plurality of AL SEN transistors to horizontally bin together floating diffusions of the first portion on a row-by-row basis of the pixel array. ### Claim 14 (depends on 13) The method according to claim 13, wherein the plurality of binning transistors includes a plurality of VNG transistors, wherein, in the first binning mode, the control circuitry controls the plurality of VNG transistors to vertically bin together the floating diffusions of the first portion on a column-by-column basis of the pixel array. ### Claim 15 (depends on 9) The method according to claim 9, wherein the first mode is a first binning mode and the second mode is a second binning mode, wherein the plurality of binning transistors includes a plurality of SNG transistors, and wherein, in the first binning mode, the control circuitry controls the plurality of SNG transistors to horizontally bin together sense nodes of the second portion on a row-by-row basis of the pixel array. ### Claim 16 (depends on 15) The method according to claim 15, wherein the plurality of binning transistors includes a plurality of VNG transistors, and wherein, in the first binning mode, the control circuitry controls the plurality of VNG transistors to vertically bin together the sense nodes of the second portion on a column-by-column basis of the pixel array. ### Claim 17 (depends on 9) The method according to claim 9, wherein the first mode is a first binning mode and the second mode is a second binning mode, wherein the plurality of binning transistors includes a plurality of ALSEN transistors, and wherein, in the first binning mode, the control circuitry controls the plurality of ALSEN transistors to horizontally bin together floating diffusions of the first portion on a row-by-row basis of the pixel array. ### Claim 18 (depends on 17) The method according to claim 17, wherein the plurality of binning transistors includes a plurality of VNG transistors, wherein, in the first binning mode, the control circuitry controls the plurality of VNG transistors to vertically bin together the floating diffusions of the first portion on a column-by-column basis of the pixel array. ### Claim 19 An electronic device comprising: a pixel array including a plurality of pixel circuits; and a plurality of binning transistors, wherein a first portion of the plurality of pixel circuits individually includes two or more intensity photodiodes and a second portion of the plurality of pixel circuits individually includes two or more event vision sensor (EVS) photodiodes that are separate and distinct from the two or more intensity photodiodes, and wherein the plurality of binning transistors are configured to bin together the first portion, bin together the second portion, and bin together the first portion and bin together the second portion, respectively. ### Claim 20 (depends on 19) The electronic device according to claim 19, wherein the plurality of binning transistors includes a plurality of SNG transistors that are configured to horizontally bin together sense nodes of the second portion on a row-by-row basis of the pixel array.