# US 12,003,612 B2 · Transmitting clock reference over reverse channel in a bidirectional serial link

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- Number: US 12,003,612 B2
- Document ID: US12003612B2
- Status: Granted
- Kind: B2
- Application number: 17/890,817
- Filed: 2022-08-18
- Published: 2023-03-16
- Granted: 2024-06-04
- Earliest claimed: 2021-09-10
- Assignees: Maxim Integrated Products, Inc.
- Applicants: Maxim Integrated Products, Inc.
- Inventors: Jerzy A. Teterwak
- Web page: https://patentgrep.com/patent/US12003612B2

## CPC

- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H03L 7/07: using several loops, e.g. for redundant clock signal generation
- H03L 7/0807: {concerning mainly a recovery circuit for the reference signal}
- H03L 7/0812: {and where no voltage or current controlled oscillator is used}
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H04L 7/0004: {Initialisation of the receiver (H04L7/0075 and H04L7/10 take precedence)}
- H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.

## Claims

### Claim 1

A clock recovery circuit for a serializer/deserializer comprising:
a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream;
a phase lock loop including a detector configured to receive the serial data stream and to operate as a phase/frequency detector, or a phase detector; and
a controller configured to receive the clock detect signal and to selectively enable the detector based on the clock detect signal.

### Claim 2 (depends on 1)

The clock recovery circuit of claim 1, wherein the phase lock loop further comprises a frequency divider configured to divide a clock signal and to output a divided clock signal to the detector.