# US 12,003,610 B1 · Retimer with mesochronous intra-lane path controllers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,003,610 B1 - Document ID: US12003610B1 - Status: Granted - Kind: B1 - Application number: 17/724,207 - Filed: 2022-04-19 - Granted: 2024-06-04 - Earliest claimed: 2019-09-20 - Assignees: Astera Labs, Inc. - Applicants: Astera Labs, Inc. - Inventors: Enrique Musoll; Casey Morrison; Ken (Keqin) Han; Pulkit Khandelwal; Subbarao Arumilli - Web page: https://patentgrep.com/patent/US12003610B1 ## CPC - G06F 13/4295: {using an embedded synchronisation} - H04L 7/0041: {Delay of data signal} - G06F 13/4291: {using a clocked protocol} - H04L 25/03885: {adaptive} - G06F 2213/0026: PCI express - H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract First and second clock signals are generated based on signal transitions within first and second streams of symbols, respectively, received within an integrated circuit component, the first and second clock signals having a time-varying phase offset with respect to one another. A first control circuit, operating in a first timing domain established by the first clock signal, generates first control information based on the first stream of symbols and forwards the first control information, via a domain crossing circuit that bridges the time-varying phase offset, to a second control circuit operating in a second timing domain. The second control circuit generates a third stream of symbols based on the first control information and on the second stream of symbols, and a transmit circuit outputs the third stream of symbols from the integrated circuit component synchronously with respect to the second clock signal. ## Claims ### Claim 1 A retimer integrated circuit (IC) comprising: a first signaling interface to concurrently receive a plurality of symbol streams; clock recovery circuitry to recover respective clock signals from the plurality of symbol streams; clock selection circuitry to select a first clock signal from the respective clock signals; and a second signaling interface to concurrently output, from the retimer IC at times indicated by the first clock signal, two or more symbol streams of the plurality of symbol streams; wherein the first signaling interface to concurrently receive the plurality of symbol streams concurrently comprises circuitry to receive the symbol streams via respective signaling lanes; wherein the clock selection circuitry to select the first clock signal from the respective clock signals comprises circuitry to select the first clock signal based at least in part on lane-aggregation information that indicates aggregation of one of more subsets of the plurality of lanes into one or more multi-lane communication channels, respectively. ### Claim 2 (depends on 1) The retimer IC of claim 1 wherein the clock recovery circuitry to recover respective clock signals from the plurality of symbol streams comprises clock-data-recovery circuitry to synthesize, for each individual symbol stream of the plurality of symbol streams, a respective one of the clock signals based on signal transitions within the individual symbol stream. ### Claim 3 (depends on 1) The retimer IC of claim 1 wherein the circuitry to select the first clock signal based at least in part on the lane-aggregation information comprises multiplexer circuitry having inputs to receive the respective clock signals and an output to output the first clock signal. ### Claim 4 (depends on 1) The retimer IC of claim 1 further comprising a programmable configuration circuit of the retimer IC and circuitry to store the lane-aggregation information within the programmable configuration circuit. ### Claim 5 (depends on 4) The retimer IC of claim 4 wherein the circuitry to store the lane-aggregation information within the programmable configuration circuit additionally stores, for a first multi-lane communication channel of the one or more multi-lane communication channels, a clock selection value within the programmable configuration circuit, and wherein the clock selection circuitry to select the first clock signal from the respective clock signals comprises circuitry to select the first clock signal from a subset of the respective clock signals in accordance with the clock selection value, the subset of the respective clock signals being indicated by the lane-aggregation information. ### Claim 6 A retimer integrated circuit (IC) comprising: a first signaling interface to concurrently receive a plurality of symbol streams; clock recovery circuitry to recover respective clock signals from the plurality of symbol streams; clock selection circuitry to select a first clock signal from the respective clock signals; a second signaling interface to concurrently output, from the retimer IC at times indicated by the first clock signal, two or more symbol streams of the plurality of symbol streams; and a programmable register, and wherein the clock selection circuitry to select the first clock signal from the respective clock signals comprises circuitry to select the first clock signal in accordance with an aggregation value and a clock-selection value stored within respective fields of the programmable register, the aggregation value indicating a subset, fewer than all, of the respective clock signals recovered from a corresponding subset of the plurality of symbol streams, and the clock-selection value specifying selection, as the first clock signal, of one clock signal from among the subset of the respective clock signals. ### Claim 7 (depends on 1) The retimer IC of claim 1 wherein the respective clock signals recovered from the plurality of symbol streams are mesochronous with respect to one another. ### Claim 8 (depends on 1) The retimer IC of claim 1 wherein each symbol stream of the plurality of symbols streams conveys fixed-length blocks of data and ordered-set blocks in compliance with a Peripheral Component Interconnect Express (PCIe) specification. ### Claim 9 A method of operation within an integrated-circuit retimer (retimer IC), the method comprising: receiving a plurality of symbol streams concurrently via a first signaling interface; recovering respective clock signals from the plurality of symbol streams; selecting a first clock signal from the respective clock signals; and outputting from the retimer IC, concurrently via a second signaling interface, two or more symbol streams of the plurality of symbol streams at times indicated by the first clock signal; wherein receiving the plurality of symbol streams concurrently comprises receiving the symbol streams via respective signaling lanes coupled to the first signaling interface; wherein selecting the first clock signal from the respective clock signals comprises selecting the first clock signal based at least in part on lane-aggregation information that indicates aggregation of one of more subsets of the plurality of lanes into one or more multi-lane communication channels, respectively. ### Claim 10 (depends on 9) The method of claim 9 wherein recovering respective clock signals from the plurality of symbol streams comprises synthesizing, for each individual symbol stream of the plurality of symbol streams, a respective one of the clock signals based on signal transitions within the individual symbol stream. ### Claim 11 (depends on 9) The method of claim 9 further comprising storing the lane-aggregation information within a programmable configuration circuit of the retimer IC. ### Claim 12 (depends on 11) The method of claim 11 further comprising storing, for a first multi-lane communication channel of the one or more multi-lane communication channels, a clock selection value within the programmable configuration circuit, and wherein selecting the first clock signal from the respective clock signals comprises selecting the first clock signal from a subset of the respective clock signals in accordance with the clock selection value, the subset of the respective clock signals being indicated by the lane-aggregation information. ### Claim 13 A method of operation within an integrated-circuit retimer (retimer IC), the method comprising: receiving a plurality of symbol streams concurrently via a first signaling interface; recovering respective clock signals from the plurality of symbol streams; selecting a first clock signal from the respective clock signals; and outputting from the retimer IC, concurrently via a second signaling interface, two or more symbol streams of the plurality of symbol streams at times indicated by the first clock signal; wherein selecting the first clock signal from the respective clock signals comprises selecting the first clock signal in accordance with an aggregation value and a clock-selection value stored within respective fields of a programmable register of the retimer IC, the aggregation value indicating a subset, fewer than all, of the respective clock signals recovered from a corresponding subset of the plurality of symbol streams, and the clock-selection value specifying selection, as the first clock signal, of one clock signal from among the subset of the respective clock signals. ### Claim 14 (depends on 9) The method of claim 9 wherein the respective clock signals recovered from the plurality of symbol streams are mesochronous with respect to one another. ### Claim 15 (depends on 9) The method of claim 9 wherein each symbol stream of the plurality of symbols streams conveys fixed-length blocks of data and ordered-set blocks in compliance with a Peripheral Component Interconnect Express (PCIe) specification.