# US 12,003,275 B2 · Clock synchronization apparatus, optical transmitter, optical receiver, and clock synchronization method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,003,275 B2 - Document ID: US12003275B2 - Status: Granted - Kind: B2 - Application number: 17/645,198 - Filed: 2021-12-20 - Published: 2022-04-14 - Granted: 2024-06-04 - Earliest claimed: 2019-06-21 - Assignees: Huawei Technologies Co., Ltd. - Applicants: Huawei Technologies Co., Ltd. - Inventors: Jun Chen; Zhuhong Zhang; Chuandong Li; Jin Wan; Zhikui Yong - Web page: https://patentgrep.com/patent/US12003275B2 ## CPC - H04B 10/40: Transceivers - H04B 10/079: using measurements of the data signal - H04B 10/50: Transmitters - H04B 10/60: Receivers - H04L 7/0025: {interpolation of clock signal} - H04L 7/0041: {Delay of data signal} - H04L 7/0075: {with photonic or optical means} - H04B: TRANSMISSION - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A clock synchronization apparatus, an optical transmitter, an optical receiver, and a clock synchronization method are provided. In the clock synchronization apparatus, a digital interpolator adjusts a sampling clock frequency of a digital signal under sampling clock control of a clock control circuit. ## Claims ### Claim 1 An optical transmitter, comprising: a digital interpolator; a digital delay element; and a clock control circuit; wherein the digital interpolator is configured to perform sampling clock adjustment on a received first digital signal under phase control of the clock control circuit, to obtain a second optical digital signal; wherein the digital delay element is configured to delay the second optical digital signal, to obtain a third optical digital signal; and wherein the clock control circuit is configured to: detect sampling clocks of the second optical digital signal and the third optical digital signal, to obtain a sampling clock deviation; generate a clock control signal based on the sampling clock deviation; and perform sampling clock control on the digital interpolator based on the clock control signal. ### Claim 2 (depends on 1) The optical transmitter according to claim 1, wherein the clock control circuit comprises: a phase detector, configured to detect the second optical digital signal and the third optical digital signal, to obtain the sampling clock deviation; and a loop controller, configured to generate the clock control signal based on the sampling clock deviation. ### Claim 3 (depends on 2) The optical transmitter according to claim 2, wherein the digital delay element is a first in first out (FIFO) delay memory. ### Claim 4 (depends on 3) The optical transmitter according to claim 3, further comprising: a digital sampler, configured to perform time-domain up-sampling on the third optical digital signal obtained by the digital delay element, to obtain a fourth optical digital signal; a phase-locked loop, configured to generate a clock signal with a fixed sampling frequency, wherein a sampling frequency of the fourth optical digital signal is the fixed sampling frequency; and a digital-to-analog converter, configured to convert the fourth optical digital signal into an analog signal based on the clock signal. ### Claim 5 (depends on 2) The optical transmitter according to claim 2, further comprising: a digital sampler, configured to perform time-domain up-sampling on the third optical digital signal obtained by the digital delay element, to obtain a fourth optical digital signal; a phase-locked loop, configured to generate a clock signal with a fixed sampling frequency, wherein a sampling frequency of the fourth optical digital signal is the fixed sampling frequency; and a digital-to-analog converter, configured to convert the fourth optical digital signal into an analog signal based on the clock signal. ### Claim 6 (depends on 1) The optical transmitter according to claim 1, wherein the digital delay element is a first in first out (FIFO) delay memory. ### Claim 7 (depends on 6) The optical transmitter according to claim 6, further comprising: a digital sampler, configured to perform time-domain up-sampling on the third optical digital signal obtained by the digital delay element, to obtain a fourth optical digital signal; a phase-locked loop, configured to generate a clock signal with a fixed sampling frequency, wherein a sampling frequency of the fourth optical digital signal is the fixed sampling frequency; and a digital-to-analog converter, configured to convert the fourth optical digital signal into an analog signal based on the clock signal. ### Claim 8 (depends on 1) The optical transmitter according to claim 1, further comprising: a digital sampler, configured to perform time-domain upsampling on the third optical digital signal obtained by the digital delay element, to obtain a fourth optical digital signal; a phase-locked loop, configured to generate a clock signal with a fixed sampling frequency, wherein a sampling frequency of the fourth optical digital signal is the fixed sampling frequency; and a digital-to-analog converter, configured to convert the fourth optical digital signal into an analog signal based on the clock signal. ### Claim 9 An optical receiver, comprising: a phase-locked loop, configured to generate a clock signal with a fixed sampling frequency; an analog-to-digital converter, configured to convert a received analog signal into a third digital signal based on the clock signal; a digital sampler, configured to perform time-domain downsampling on the third digital signal, to obtain a first digital signal; a clock control circuit; and a digital interpolator, configured to perform sampling clock adjustment on the first digital signal under sampling clock control of the clock control circuit, to obtain a second digital signal; and wherein the clock control circuit is configured to: generate a timing recovery control signal based on the second digital signal; and perform sampling clock control on the digital interpolator based on the timing recovery control signal. ### Claim 10 (depends on 9) The optical receiver according to claim 9, wherein the clock control circuit comprises: a timing recovery circuit, configured to obtain a timing recovery clock signal based on the second digital signal; and a loop controller, configured to generate the timing recovery control signal based on the timing recovery clock signal. ### Claim 11 (depends on 9) The optical receiver according to claim 9, wherein the digital interpolator comprises a time-domain finite impulse response (FIR) filter. ### Claim 12 (depends on 9) The optical receiver according to claim 9, wherein the digital interpolator comprises a frequency-domain delay multiplier. ### Claim 13 (depends on 9) The optical receiver according to claim 9, wherein the clock control circuit is configured to extract a timing offset based on the second digital signal, and generate a timing recovery clock signal based on the timing offset. ### Claim 14 (depends on 9) The optical receiver according to claim 9, wherein the phase-locked loop is an integer phase-locked loop (IPLL). ### Claim 15 (depends on 9) The optical receiver according to claim 9, wherein the phase-locked loop is a fraction phase-locked loop (FPLL). ### Claim 16 An optical transceiver apparatus, comprising: an optical transmitter; and an optical receiver; wherein the optical transmitter comprises a first digital interpolator, a digital delay element, and a first clock control circuit; wherein the first digital interpolator is configured to perform sampling clock adjustment on a received first digital signal under phase control of the first clock control circuit, to obtain a second optical digital signal; wherein the digital delay element is configured to delay the second optical digital signal, to obtain a third optical digital signal; wherein the first clock control circuit is configured to: detect sampling clocks of the second optical digital signal and the third optical digital signal, to obtain a sampling clock deviation; generate a clock control signal based on the sampling clock deviation; and perform sampling clock control on the first digital interpolator based on the clock control signal; wherein the optical receiver comprises a second digital interpolator and a second clock control circuit; wherein the second digital interpolator is configured to perform sampling clock adjustment on a received fifth digital signal under sampling clock control of the second clock control circuit, to obtain a sixth digital signal; and wherein the second clock control circuit is configured to: generate a timing recovery control signal based on the sixth digital signal; and perform sampling clock control on the second digital interpolator based on the timing recovery control signal. ### Claim 17 (depends on 16) The optical transceiver apparatus according to claim 16, wherein the first clock control circuit comprises: a phase detector, configured to detect the second optical digital signal and the third optical digital signal, to obtain the sampling clock deviation; and a loop controller, configured to generate the clock control signal based on the sampling clock deviation. ### Claim 18 (depends on 16) The optical transceiver apparatus according to claim 16, wherein the optical transmitter further comprises: a digital sampler, configured to perform time-domain upsampling on the third optical digital signal obtained by the digital delay element, to obtain a fourth optical digital signal; a phase-locked loop, configured to generate a clock signal with a fixed sampling frequency, wherein a sampling frequency of the fourth optical digital signal is the fixed sampling frequency; and a digital-to-analog converter, configured to convert the fourth optical digital signal into an analog signal based on the clock signal. ### Claim 19 (depends on 16) The optical transceiver apparatus according to claim 16, wherein the optical receiver further comprises: a phase-locked loop, configured to generate a clock signal with a fixed sampling frequency; an analog-to-digital converter, configured to convert a received analog signal into a seventh digital signal based on the clock signal; and a digital sampler, configured to perform time-domain downsampling on the seventh digital signal to obtain the fifth digital signal.