# US 12,003,255 B2 · Method and device for binary coding of signals in order to implement digital MAC operations with dynamic precision > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,003,255 B2 - Document ID: US12003255B2 - Status: Granted - Kind: B2 - Application number: 17/787,300 - Filed: 2020-12-10 - Published: 2023-01-19 - Granted: 2024-06-04 - Earliest claimed: 2019-12-18 - Assignees: Commissariat A L'energie Atomique Et Aux Energies Alternatives - Applicants: Commissariat A L'energie Atomique Et Aux Energies Alternatives - Inventors: Johannes Christian Thiele; Olivier Bichler; Marc Duranton; Vincent Lorrain - Web page: https://patentgrep.com/patent/US12003255B2 ## CPC - H03M 7/04: the radix thereof being two - H03M 7/28: Programmable structures, i.e. where the code converter contains apparatus which is operator-changeable to modify the conversion process - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G06N 3/02: Neural networks - G06N 3/048: Activation functions - G06F 17/18: for evaluating statistical data {, e.g. average values, frequency distributions, probability functions, regression analysis (forecasting specially adapted for a specific administrative, business or logistic context G06Q10/04)} - G06F 2207/4824: Neural networks - G06N 3/063: using electronic means - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A computer-implemented method for coding a digital signal intended to be processed by a digital computing system includes the steps of: receiving a sample of the digital signal quantized on a number Nd of bits, decomposing the sample into a plurality of binary words of parameterizable bit size Np, coding the sample through a plurality of pairs of values, each pair comprising one of the binary words and an address corresponding to the position of the binary word in the sample, transmitting the pairs of values to an integration unit in order to carry out a MAC operation between the sample and a weighting coefficient. ## Claims ### Claim 1 A computer-implemented method for coding a digital signal intended to be processed by a digital computing system, the method comprising the steps of: receiving a sample of the digital signal quantized on a number Nd of bits, decomposing the sample into a plurality of binary words of parameterizable bit size Np, coding the sample through a plurality of pairs of values, each pair comprising one of the binary words and an address corresponding to the position of the binary word in the sample, transmitting the pairs of values to an integration unit in order to carry out a MAC operation between the sample and a weighting coefficient. ### Claim 2 (depends on 1) The coding method as claimed in claim 1, wherein only pairs of values comprising non-zero binary words are transmitted. ### Claim 3 (depends on 1) The coding method as claimed in claim 1, comprising a step of deleting zero binary words before carrying out the MAC operation. ### Claim 4 (depends on 1) The coding method as claimed in claim 1, wherein one and the same address corresponding to binary words coded from various samples is transmitted only once. ### Claim 5 (depends on 1) The coding method as claimed in claim 1, comprising a step of determining the size Np of a binary word based on the statistical distribution of the values at 0 of the bits of the digital signal. ### Claim 6 (depends on 5) The coding method as claimed in claim 5, wherein the size Np of a binary word is parameterized so as to minimize the energy consumption of a digital computing system wherein the processed signals are coded by way of said coding method. ### Claim 7 (depends on 6) The coding method as claimed in claim 6, wherein the energy consumption is estimated by simulation or on the basis of an empirical model. ### Claim 8 (depends on 1) The coding method as claimed in claim 1, wherein the digital computing system implements an artificial neural network. ### Claim 9 (depends on 8) The coding method as claimed in claim 8, wherein the size Np of the binary words is parameterized independently for each layer of the artificial neural network. ### Claim 10 (depends on 1) A coding device comprising a coder configured to execute the coding method as claimed in claim 1. ### Claim 11 (depends on 1) An integration device configured to carry out a multiply-accumulate (MAC) operation between a first number coded by way of the coding method as claimed in claim 1 and a weighting coefficient, the device comprising a multiplier (MUL) for multiplying the weighting coefficient by the binary word of the first number, a shift register (REG) configured to shift the output signal from the multiplier (MUL) by the value of the address of said binary word, an adder (ADD) and an accumulation register (RAC) for accumulating the output signal from the shift register (REG). ### Claim 12 (depends on 11) An artificial neuron (N), implemented by a digital computing system, comprising an integration device as claimed in claim 11 for carrying out a multiply-accumulate (MAC) operation between a received signal and a synaptic coefficient, and a coding device comprising a coder configured to execute the coding method as claimed in claim 11 for coding the output signal from the integration device the artificial neuron (N) being configured to propagate the coded signal to another artificial neuron. ### Claim 13 (depends on 11) An artificial neuron (N), implemented by a computer, comprising an integration device as claimed in claim 11 for carrying out a multiply-accumulate (MAC) operation between an error signal received from another artificial neuron and a synaptic coefficient, a local error computing module configured to compute a local error signal on the basis of the output signal from the integration device and a coding device comprising a coder configured to execute the coding method as claimed in claim 11 for coding the local error signal, the artificial neuron (N) being configured to back-propagate the local error signal to another artificial neuron. ### Claim 14 (depends on 12) An artificial neural network comprising a plurality of artificial neurons as claimed in claim 12.