# US 12,003,252 B2 · Error correcting code poisoning for memory devices and associated methods and systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,003,252 B2 - Document ID: US12003252B2 - Status: Granted - Kind: B2 - Application number: 18/084,048 - Filed: 2022-12-19 - Published: 2023-04-20 - Granted: 2024-06-04 - Earliest claimed: 2020-11-09 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Joshua E. Alzheimer; Randall J. Rooney - Web page: https://patentgrep.com/patent/US12003252B2 ## CPC - H03M 13/015: {Simulation or testing of codes, e.g. bit error rate [BER] measurements} - H03M 13/05: using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to poison data based on an indication provided by a host device coupled with the memory devices. The indication may include which one or more bits to poison (invert) at which stages of performing write or read operations. In some embodiments, the memory device may invert one or more bits according to the indication and then correct one or more errors associated with inverting the one or more bit to verify its on-die ECC functionality. In some embodiments, the memory device may provide the host device with poisoned data including one or more bits inverted according to the indication such that the host device may test system-level ECC functionality using the poisoned data. ## Claims ### Claim 1 A method, comprising: receiving, at a memory device, a command from a host device coupled with the memory device, the command directed to a first data set; generating, from the first data set, a second data set by inverting one or more bits of the first data set, wherein inverting the one or more bits of the first data set is based at least in part on one or more predetermined poisoned bit locations indicated to the memory device; detecting one or more errors in the second data set based, at least in part, on the one or more inverted bits; correcting the one or more errors in the second data set to generate a third data set comprising bits that match the first data set; and transmitting, to the host device, the third data set generated from the second data set and comprising the bits that match the first data set. ### Claim 2 (depends on 1) The method of claim 1, wherein one or more registers of the memory device are configured to store the one or more predetermined poisoned bit locations. ### Claim 3 (depends on 1) The method of claim 1, wherein the one or more predetermined poisoned bit locations are indicated to the memory device through one or more commands to program a register of the memory device transmitted from the host device to the memory device, prior to receiving the command. ### Claim 4 (depends on 1) The method of claim 1, wherein the command corresponds to a write command providing the first data set, and generating the second data set from the first data set further comprises: calculating error correcting code (ECC) check bits using the first data set, wherein the second data set includes the first data set and the ECC check bits; and inverting the one or more bits of the second data set corresponding to the one or more predetermined poisoned bit locations. ### Claim 5 (depends on 4) The method of claim 4, further comprising: writing the second data set to a memory array of the memory device, the write command including an address of the memory array to write the second data set. ### Claim 6 (depends on 5) The method of claim 5, further comprising: receiving a read command from the host device, the read command including the address; and reading, in response to receiving the read command, the second data set from the memory array, wherein detecting the one or more errors in the second data set corresponds to detecting the one or more errors in the second data set read from the memory array. ### Claim 7 (depends on 1) The method of claim 1, wherein the command corresponds to a read command reading the first data set from a memory array of the memory device, and generating the second data set from the first data set further comprises: reading the first data set and a first group of ECC check bits from an address of the memory array included in the read command, the first group of ECC check bits calculated using the first data set; and inverting the one or more bits of the first data set and the first group of ECC check bits read from the memory array, the one or more bits corresponding to the one or more predetermined poisoned bit locations, wherein the second data set includes the first data set and the first group of ECC check bits with the one or more inverted bits. ### Claim 8 (depends on 7) The method of claim 7, further comprising: calculating a second group of ECC check bits using the second data set; and comparing the first group of ECC check bits with the second group of ECC check bits. ### Claim 9 (depends on 8) The method of claim 8, wherein detecting the one or more errors in the second data set is based, at least in part, on comparing the first group of ECC check bits with the second group of ECC check bits. ### Claim 10 A method, comprising: receiving, at a memory device, a command from a host device coupled with the memory device, the command directed to a first data set; inverting one or more bits of the first data set based on one or more predetermined poisoned bit locations indicated to the memory device; and transmitting the first data set with the one or more inverted bits to the host device. ### Claim 11 (depends on 10) The method of claim 10, wherein the command corresponds to a write command providing the first data set, the method further comprising: calculating a group of error correcting code (ECC) check bits using the first data set with the one or more inverted bits; and writing the first data set with the one or more inverted bits and the group of ECC check bits to an address of a memory array of the memory device, the write command including the address. ### Claim 12 (depends on 11) The method of claim 11, further comprising: receiving, after writing the first data set with the one or more inverted bits to the address, a read command from the host device, the read command including the address; and reading, in response to receiving the read command, the first data set with the one or more inverted bits from the memory array, wherein transmitting the first data set with the one or more inverted bits corresponds to transmitting the first data set with the one or more inverted bits read from the memory array. ### Claim 13 (depends on 12) The method of claim 12, wherein the group of ECC check bits is a first group of ECC check bits, the method further comprising: calculating a second group of ECC check bits using the first data set with the one or more inverted bits read from the memory array; and comparing the first group of ECC check bits and the second group of ECC check bits, prior to transmitting the first data set with the one or more inverted bits to the host device. ### Claim 14 (depends on 10) The method of claim 10, wherein the command corresponds to a read command reading the first data set from a memory array of the memory device, the method further comprising: reading the first data set and a first group of ECC check bits from an address of the memory array included in the read command, the first group of ECC check bits calculated using the first data set; calculating a second group of ECC check bits using the first data set read from the memory array; and comparing the first group of ECC check bits with the second group of ECC check bits. ### Claim 15 (depends on 14) The method of claim 14, wherein inverting the one or more bits of the first data set corresponds to inverting the one or more bits of the first data set read from the memory array, after comparing the first group of ECC check bits with the second group of ECC check bits. ### Claim 16 An apparatus, comprising: a memory array; and peripheral circuitry coupled with the memory array, the peripheral circuitry configured to: receive a command from a host device coupled with the apparatus, the command directed to a first data set; generate, from the first data set, a second data set by inverting one or more bits of the first data set, wherein inverting the one or more bits of the first data set is based at least in part on one or more predetermined poisoned bit locations indicated to the apparatus; and transmitting, to the host device, the second data set. ### Claim 17 (depends on 16) The apparatus of claim 16, further comprising: one or more registers configured to store the one or more predetermined poisoned bit locations. ### Claim 18 (depends on 16) The apparatus of claim 16, further comprising: a command decoder configured to determine the one or more predetermined poisoned bit locations based, at least in part, on one or more commands to program a register of the apparatus transmitted from the host device. ### Claim 19 (depends on 16) The apparatus of claim 16, wherein the peripheral circuitry is further configured to: calculate error correcting code (ECC) check bits using the first data set provided with a write command from the host device, wherein the second data set includes the first data set and the ECC check bits; and invert the one or more bits of the second data set corresponding to the one or more predetermined poisoned bit locations. ### Claim 20 (depends on 16) The apparatus of claim 16, wherein the peripheral circuitry is further configured to: read the first data set and a first group of ECC check bits from an address of the memory array included in a read command from the host device, the first group of ECC check bits calculated using the first data set; and invert the one or more bits of the first data set and the first group of ECC check bits read from the memory array, the one or more bits corresponding to the one or more predetermined poisoned bit locations, wherein the second data set includes the first data set and the first group of ECC check bits with the one or more bits inverted.