# US 12,003,250 B2 · Digital-to-analog converter including current cell array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,003,250 B2 - Document ID: US12003250B2 - Status: Granted - Kind: B2 - Application number: 17/837,752 - Filed: 2022-06-10 - Published: 2022-12-15 - Granted: 2024-06-04 - Earliest claimed: 2021-06-10 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Kyeongjoon Ko; Jaehyun Park; Junhan Bae; Gyeongseok Song; Jongjae Ryu - Web page: https://patentgrep.com/patent/US12003250B2 ## CPC - H03M 1/682: {both converters being of the unary decoded type} - H03M 1/687: {Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type} - H03M 1/747: {with equal currents which are switched by unary decoded digital signals} - H03M 1/0617: {characterised by the use of methods or means not specific to a particular type of detrimental influence} - H03M 1/66: Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A digital-to-analog converter includes a current cell array including a plurality of current cells, each current cell of the plurality of current cells being configured to generate a current of a same magnitude; a first pattern connecting first current cells, among the plurality of current cells, arranged along a diagonal line of the current cell array; a second pattern connecting second current cells, among the plurality of current cells, arranged along a first oblique line parallel to the diagonal line; and a third pattern connecting third current cells, among the plurality of current cells, arranged along a second oblique line parallel to the diagonal line, the third pattern being electrically connected to the second pattern, wherein the diagonal line is between the first oblique line and the second oblique line. ## Claims ### Claim 1 A digital-to-analog converter comprising: a current cell array comprising a plurality of current cells, each current cell of the plurality of current cells being configured to generate a current of a same magnitude; a first pattern connecting first current cells, among the plurality of current cells, arranged along a diagonal line of the current cell array; a second pattern connecting second current cells, among the plurality of current cells, arranged along a first oblique line parallel to the diagonal line; and a third pattern connecting third current cells, among the plurality of current cells, arranged along a second oblique line parallel to the diagonal line, the third pattern being electrically connected to the second pattern, wherein the diagonal line is between the first oblique line and the second oblique line and wherein the second current cells and the third current cells are arranged with no second current cell and third current cell in a same row and with no second current cell and third current cell in a same column. ### Claim 2 (depends on 1) The digital-to-analog converter of claim 1, wherein the plurality of current cells are arranged in K rows and K columns in the current cell array, K being an integer greater than 1, and a sum of a first number of the second current cells and a second number of the third current cells is equal to K. ### Claim 3 (depends on 1) The digital-to-analog converter of claim 1, wherein a digital input of the digital-to-analog converter is N bits, N being an integer greater than 1, and currents generated by the first current cells are used for generation of an analog output of the digital-to-analog converter when a value of the digital input is equal to or greater than 2N-1. ### Claim 4 (depends on 1) The digital-to-analog converter of claim 1, further comprising a decoder configured to generate a thermometer code from an upper bit group comprising a most significant bit (MSB) of a digital input of the digital-to-analog converter, wherein the first current cells correspond to a first bit of the thermometer code, and the second current cells and the third current cells commonly correspond to a second bit of the thermometer code. ### Claim 5 (depends on 4) The digital-to-analog converter of claim 4, wherein the plurality of current cells comprises fourth current cells and fifth current cells corresponding to a lower bit group comprising a least significant bit of the digital input, the fourth current cells are arranged along a third oblique line parallel to the diagonal line, the fifth current cells are arranged along a fourth oblique line parallel to the diagonal line, and the diagonal line is between the third oblique line and the fourth oblique line. ### Claim 6 (depends on 5) The digital-to-analog converter of claim 5, wherein the fourth current cells and the fifth current cells are arranged with no fourth current cell and fifth current cell in a same row and with no fourth current cell and fifth current cell in a same column. ### Claim 7 (depends on 5) The digital-to-analog converter of claim 5, wherein the third oblique line and the fourth oblique line respectively correspond to a first diagonal line of a first quadrant of the current cell array and a second diagonal line of a second quadrant of the current cell array. ### Claim 8 (depends on 1) The digital-to-analog converter of claim 1, wherein each current cell of the plurality of current cells comprises a first transistor and a second transistor that are connected in series and are respectively biased by a first voltage and a second voltage. ### Claim 9 (depends on 1) The digital-to-analog converter of claim 1, wherein the first pattern is configured to connect every current cell of the first current cells arranged along the diagonal line and no other current cells, and wherein the diagonal line is a main diagonal of the current cell array. ### Claim 10 A digital-to-analog converter comprising: a decoder configured to generate a thermometer code from an upper bit group comprising a most significant bit (MSB) of a digital input of the digital-to-analog converter; a current cell array comprising a plurality of current cells, each current cell of the plurality of current cells being configured to generate a current of a same magnitude; and a switch circuit configured to select at least a part of currents generated by the current cell array, wherein the plurality of current cells comprises: first current cells arranged along a diagonal line of the current cell array and corresponding to a first bit of the thermometer code; second current cells arranged along a first oblique line parallel to the diagonal line and corresponding to a second bit of the thermometer code; and third current cells arranged along a second oblique line parallel to the diagonal line and corresponding to the second bit of the thermometer code, and wherein the diagonal line is between the first oblique line and the second oblique line. ### Claim 11 (depends on 10) The digital-to-analog converter of claim 10, wherein the second current cells and the third current cells are arranged with no second current cell and third current cell in a same row and with no second current cell and third current cell in a same column. ### Claim 12 (depends on 10) The digital-to-analog converter of claim 10, wherein the digital input is N bits, N being an integer greater than 1, and currents generated by the first current cells are selected by the switch circuit when a value of the digital input is equal to or greater than 2N-1. ### Claim 13 (depends on 10) The digital-to-analog converter of claim 10, wherein the plurality of current cells comprises fourth current cells and fifth current cells corresponding to a lower bit group comprising a least significant bit of the digital input, the fourth current cells are arranged along a third oblique line parallel to the diagonal line, the fifth current cells are arranged along a fourth oblique line parallel to the diagonal line, and the diagonal line is between the third oblique line and the fourth oblique line. ### Claim 14 (depends on 13) The digital-to-analog converter of claim 13, wherein the fourth current cells and the fifth current cells are arranged with no fourth current cell and fifth current cell in a same row and with no fourth current cell and fifth current cell in a same column. ### Claim 15 (depends on 13) The digital-to-analog converter of claim 13, wherein the third oblique line and the fourth oblique line respectively correspond to a first diagonal of a first quadrant and a second diagonal of a second quadrant of the current cell array. ### Claim 16 A method of converting a digital input into an analog output, the method comprising: generating a thermometer code from an upper bit group comprising a most significant bit (MSB) of the digital input; generating a reference current by a current cell array comprising a plurality of current cells, wherein each current cell of the plurality of current cells is configured to generate a current of a same magnitude; selecting at least a part of the reference current, based on the thermometer code and a lower bit group comprising a least significant bit of the digital input; and generating the analog output by summing a selected current, wherein the selecting the at least the part of the reference current comprises selecting currents generated by first current cells, among the plurality of current cells, arranged with no two first current cells in a same row and with no two first current cells in a same column, based on one bit of the thermometer code. ### Claim 17 (depends on 16) The method of claim 16, wherein the first current cells are arranged along a diagonal line of the current cell array or along a first oblique line and a second oblique line that are parallel to the diagonal line. ### Claim 18 (depends on 17) The method of claim 17, wherein the digital input is of N bits, N being an integer greater than 1, and the selecting the at least the part of the reference current comprises selecting currents generated by the first current cells arranged along the diagonal line when a value of the digital input is equal to or greater than 2N-1. ### Claim 19 (depends on 16) The method of claim 16, wherein the selecting the at least the part of the reference current comprises selecting at least a part of currents generated by second current cells, among the plurality of current cells, arranged along a third oblique line parallel to a diagonal line of the current cell array and third current cells, among the plurality of current cells, arranged along a fourth oblique line parallel to the diagonal line, based on the lower bit group, and the diagonal line is between the third oblique line and the fourth oblique line. ### Claim 20 (depends on 19) The method of claim 19, wherein the third oblique line and the fourth oblique line respectively correspond to diagonal lines of quadrants of the current cell array.