# US 12,003,248 B2 · Transceiver and method and system for controlling an analog-to-digital converter in an observation path in the transceiver

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- Number: US 12,003,248 B2
- Document ID: US12003248B2
- Status: Granted
- Kind: B2
- Application number: 17/131,819
- Filed: 2020-12-23
- Published: 2022-06-23
- Granted: 2024-06-04
- Earliest claimed: 2020-12-23
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Matteo Camponeschi; Albert Molina; Kannan Rajamani; Giacomo Cascio; Christian Lindholm
- Web page: https://patentgrep.com/patent/US12003248B2

## CPC

- H03M 1/1009: {Calibration}
- H03M 1/1265: {Non-uniform sampling}
- H04B 1/0003: {Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain (digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00)}
- H04B 1/40: Circuits
- H04L 5/0048: {Allocation of pilot signals, i.e. of signals known to the receiver (allocation of control signalling H04L5/0053; use of control signalling H04L5/0091)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04B: TRANSMISSION
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A method and system for controlling an analog-to-digital converter (ADC) in an observation path in a transceiver. The transceiver includes a transmit path, a receive path, and an observation path. The observation path includes an analog buffer and an observation ADC. A controller generates a control signal to control sampling events at the observation ADC to activate the observation ADC at combined uniform and non-uniform sampling instants. The controller may also generate a second control signal indicating whether digital data obtained by the observation ADC is valid or not. The digital data generated by the observation ADC at non-uniform sampling instants is indicated as invalid and digital data generated by the observation ADC at uniform sampling instants is indicated as valid. The digital data indicated as invalid may be discarded and the digital data indicated as valid is used for calibration of the transmit path or the receive path.

## Claims

### Claim 1

A transceiver comprising:
a transmit path including circuitries configured to process a transmit signal;
a receive path including circuitries configured to process a receive signal;
an observation path including circuitries configured to supply a reference signal for calibration of the transmit path and/or the receive path, wherein the observation path includes:
an analog buffer configured to supply a signal sensed from the transmit path or the receive path; and
an observation analog-to-digital converter (ADC) configured to digitize the signal supplied from the analog buffer, and
a controller configured to generate a first control signal to control sampling events at the observation ADC and send the first control signal to the observation ADC to activate the observation ADC at combined uniform and non-uniform sampling instants.

### Claim 2 (depends on 1)

The transceiver of claim 1, wherein the controller is configured to generate a second control signal indicating whether digital data obtained by the observation ADC is valid or not, wherein digital data generated by the observation ADC at non-uniform sampling instants is indicated as invalid and digital data generated by the observation ADC at uniform sampling instants is indicated as valid.

### Claim 3 (depends on 2)

The transceiver of claim 2, wherein the observation path further includes a circuitry configured to discard the digital data indicated as invalid and forward the digital data indicated as valid to a non-linear equalizer in the receive path or to a digital pre-distortion circuitry in the transmit path based on the second control signal.

### Claim 4 (depends on 1)

The transceiver of claim 1, wherein the controller is configured to add a random delay value to a fixed sampling period at every predetermined number of sampling instants to generate the first control signal.

### Claim 5 (depends on 4)

The transceiver of claim 4, wherein the controller includes a linear feedback shift register (LFSR) to generate the random delay value.

### Claim 6 (depends on 1)

The transceiver of claim 1, wherein the controller is configured to activate the observation ADC at a fraction of sampling rate of an ADC in a main receive path or a digital-to-analog converter (DAC) in a transmit path.

### Claim 7 (depends on 2)

The transceiver of claim 2, wherein the controller comprises:
a random delay value generation circuit configured to generate a random delay value;
a counter configured to generate an integer count value;
a logic circuit configured determine whether the integer count value is equal to a predetermined value;
a multiplexer configured to output either the random delay value or zero depending on an output of the logic circuit, wherein the random delay value is selected by the multiplexer if the integer count value is equal to the predetermined value and zero is selected by the multiplexer if the integer count value is not equal to the predetermined value; and
an adder configured to add a fixed delay value to an output of the multiplexer to generate the first control signal.

### Claim 8 (depends on 7)

The transceiver of claim 7, wherein the controller further comprises:
a second logic circuit configured to determine whether the integer count value is equal to or greater than a second predetermined value; and
a second multiplexer configured to output either zero or one as the second control signal based on an output of the second logic circuit.

### Claim 9 (depends on 7)

The transceiver of claim 7, wherein the counter is configured to generate the integer count value within a range from zero to P−1, wherein the parameter P is adjustable.

### Claim 10 (depends on 7)

The transceiver of claim 7, wherein the random delay value generation circuit is configured to generate the random delay value within a range from zero to M−1, wherein the parameter M is adjustable.

### Claim 11

A method for controlling an analog-to-digital converter (ADC) in an observation path in a transceiver, comprising:
supplying a signal sensed from a transmit path or a receive path to an observation ADC in the observation path;
generating a first control signal to control sampling events at the observation ADC;
sending the first control signal to the observation ADC to activate the observation ADC at combined uniform and non-uniform sampling instants; and
digitizing, by the observation ADC, the signal supplied based on the first control signal.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
generating a second control signal indicating whether digital data generated by the observation ADC is valid or not, wherein digital data generated by the observation ADC at non-uniform sampling instants is indicated as invalid and digital data generated by the observation ADC at uniform sampling instants is indicated as valid;
discarding the digital data indicated as invalid; and
forwarding the digital data indicated as valid to a non-linear equalizer in the receive path or to a digital pre-distortion circuitry in the transmit path.

### Claim 13 (depends on 11)

The method of claim 11, wherein the first control signal is generated by introducing a random delay value to a fixed sampling period at every predetermined number of sampling instants.

### Claim 14 (depends on 13)

The method of claim 13, wherein the random delay value is generated by a linear feedback shift register (LFSR).

### Claim 15 (depends on 11)

The method of claim 11, wherein the observation ADC is activated at a fraction of sampling rate of an ADC in a main receive path or a digital-to-analog converter (DAC) in a transmit path.

### Claim 16 (depends on 12)

The method of claim 12, wherein the first control signal is generated by:
generating a random delay value;
generating an integer count value;
determining, by a first logic circuit, whether the integer count value is equal to a predetermined value;
outputting, by a multiplexer, either the random delay value or zero depending on an output of the first logic circuit, wherein the random delay value is output if the integer count value is equal to the predetermined value and zero is output if the integer count value is not equal to the predetermined value; and
adding a fixed delay value to an output of the multiplexer to generate the first control signal.

### Claim 17 (depends on 16)

The method of claim 16, wherein the second control signal is generated by:
determining, by a second logic circuit, whether the integer count value is equal to or greater than a second predetermined value; and
outputting either zero or one as the second control signal based on an output of the second logic circuit.

### Claim 18

A system for controlling an analog-to-digital converter (ADC) in an observation path in a transceiver, comprising:
a controller configured to generate a control signal to control sampling events at an ADC and send the control signal to the ADC to activate the ADC at combined uniform and non-uniform sampling instants.

### Claim 19 (depends on 18)

The system of claim 18, wherein the controller is configured to indicate digital data generated by the ADC at non-uniform sampling instants as invalid and digital data generated by the ADC at uniform sampling instants as valid.

### Claim 20 (depends on 18)

The system of claim 18, wherein the controller comprises:
a random delay value generation circuit configured to generate a random delay value;
a counter configured to output an integer count value;
a logic circuit configured determine whether the integer count value is equal to a predetermined value;
a multiplexer configured to output either the random delay value or zero depending on an output of the logic circuit, wherein the random delay value is selected if the output of the counter is equal to the predetermined value and zero is selected if the output of the counter is not equal to the predetermined value; and
an adder configured to add a fixed delay value to an output of the multiplexer.

### Claim 21 (depends on 20)

The system of claim 20, further comprising:
a second logic circuit configured to determine whether the integer count value is equal to or greater than a second predetermined value; and
a second multiplexer configured to output either zero or one as the second control signal based on an output of the second logic circuit.

### Claim 22

A method for controlling an analog-to-digital converter (ADC) in an observation path in a transceiver, comprising:
generating a control signal to control sampling events at an ADC in the observation path in the transceiver; and
sending the control signal to the ADC to activate the ADC at combined uniform and non-uniform sampling instants.

### Claim 23 (depends on 22)

The method of claim 22, further comprising:
indicating digital data generated by the ADC at non-uniform sampling instants as invalid and indicating digital data generated by the ADC at uniform sampling instants as valid.