# US 12,003,243 B2 · Linear low side recycling modulation

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- Number: US 12,003,243 B2
- Document ID: US12003243B2
- Status: Granted
- Kind: B2
- Application number: 17/232,174
- Filed: 2021-04-16
- Published: 2021-07-29
- Granted: 2024-06-04
- Earliest claimed: 2019-05-07
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Sumit Dubey; Jasjot Singh Chadha
- Web page: https://patentgrep.com/patent/US12003243B2

## CPC

- H03K 5/06: by the use of delay lines or other analogue delay elements
- H03K 5/15: Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors (distributing, switching or gating arrangements H03K17/00)
- H03K 5/24: the characteristic being amplitude
- H03K 7/08: Duration or width modulation {; Duty cycle modulation}
- H04R 3/00: Circuits for transducers (arrangements for producing a reverberation or echo sound G10K15/08; amplifiers H03F)
- H04R 3/002: {Damping circuit arrangements for transducers, e.g. motional feedback circuits}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H04R: LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; ELECTRIC HEARING AIDS; PUBLIC ADDRESS SYSTEMS (producing sounds with frequency not determined by supply frequency G10K)

## Abstract

A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.

## Claims

### Claim 1

A circuit, comprising:
a filter having an input and an output;
a comparator having first and second inputs and an output, the first input of the comparator is coupled to the output of the filter and the second input of the comparator is configured to receive ramp signal;
a converter having an input and an output, the input of the converter is coupled to the output of the comparator;
a dual minimum pulse generator having an input and first and second outputs, the input is coupled to the output of the converter, the dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period; and
a driver having an input and an output, the input of the driver is coupled to the first output of the dual minimum pulse generator.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein responsive to the input pulse on the input of the dual minimum pulse generator having a pulse width less than the predetermined delay time period, generate a pulse on the second output of the dual minimum pulse generator that has a pulse width equal to the predetermined delay time period.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein responsive to the input pulse on the input of the dual minimum pulse generator having a pulse width greater than the predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to the predetermined delay time period.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein the dual minimum pulse generator includes:
a first pulse adder having first and second inputs and first and second outputs;
a second pulse adder having first and second inputs and first and second outputs;
a first delay cell having an input and an output, the input of the first delay cell is coupled to the second output of the first pulse adder;
a second delay cell having an input and an output, the input of the second delay cell is coupled to the second output of the second pulse adder, and the output of the second delay cell is coupled to the second input of the second pulse adder;
a first inverter having an input and an output, the input of the first inverter is coupled to the first input of the first pulse adder, and the output of the first inverter is coupled to the first input of the second pulse adder.

### Claim 5 (depends on 1)

The circuit of claim 1, further comprising a speaker coupled to the driver.

### Claim 6 (depends on 1)

The circuit of claim 1, wherein the converter is a BD-to-low side recycling converter.

### Claim 7 (depends on 1)

The circuit of claim 1, wherein the dual minimum pulse generator includes a delay cell having an input and an output, and the delay cell is configured to generate a signal on the output of the delay cell is a delayed version of a signal on the input of the delay cell, an amount of delay implemented by the delay cell being equal to the predetermined delay time period.

### Claim 8

A circuit, comprising:
a filter having an input and an output;
a comparator having first and second inputs and an output, the first input of the comparator is coupled to the output of the filter and the second input of the comparator is configured to receive ramp signal;
a converter having an input and an output, the input of the converter is coupled to the output of the comparator;
a dual minimum pulse generator having an input and first and second outputs, the input is coupled to the output of the converter; and
a driver having an input and an output, the input of the driver is coupled to the first output of the dual minimum pulse generator;
wherein the dual minimum pulse generator includes:
a first pulse adder having first and second inputs and first and second outputs;
a second pulse adder having first and second inputs and first and second outputs;
a first delay cell having an input and an output, the input of the first delay cell is coupled to the second output of the first pulse adder;
a second delay cell having an input and an output, the input of the second delay cell is coupled to the second output of the second pulse adder, and the output of the second delay cell is coupled to the second input of the second pulse adder;
a first inverter having an input and an output, the input of the first inverter is coupled to the first input of the first pulse adder, and the output of the first inverter is coupled to the first input of the second pulse adder.

### Claim 9 (depends on 8)

The circuit of claim 8, wherein responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, the circuit generates a pulse on the second output of the dual minimum pulse generator that has a pulse width equal to the predetermined delay time period.

### Claim 10 (depends on 8)

The circuit of claim 8, wherein responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width greater than a predetermined delay time period, the circuit generates a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to the predetermined delay time period.

### Claim 11 (depends on 8)

The circuit of claim 8, further comprising a speaker coupled to the driver.

### Claim 12 (depends on 8)

The circuit of claim 8, wherein the converter is a BD-to-low side recycling converter.

### Claim 13 (depends on 8)

The circuit of claim 8, wherein the dual minimum pulse generator includes a delay cell having an input and an output, and the delay cell is configured to generate a signal on the output of the delay cell that is a delayed version of a signal on the input of the delay cell, an amount of delay implemented by the delay cell being equal to the a predetermined delay time period.