# US 12,003,241 B1 · Controlling duty cycle distortion with a mixed-signal circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,003,241 B1 - Document ID: US12003241B1 - Status: Granted - Kind: B1 - Application number: 18/149,016 - Filed: 2022-12-30 - Granted: 2024-06-04 - Earliest claimed: 2022-12-30 - Assignees: Parade Technologies, Ltd. - Applicants: Parade Technologies, Ltd. - Inventors: YingFan Lee; Zhih-Ling Lu; Andrew Lee; Xin Jin - Web page: https://patentgrep.com/patent/US12003241B1 ## CPC - H03K 3/017: Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) - H03K 5/01: Shaping pulses (discrimination against noise or interference H03K5/125) - H03K 5/1565: {the output pulses having a constant duty cycle} - H03K 2005/00013: {Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Controlling Duty Cycle Distortion with a Mixed-Signal Circuit A method controls the duty cycle distortion of clock signals. An electronic device obtains an input clock signal and generates a first output voltage and a second output voltage from the input clock signal. The first output voltage has a first direct current (DC) voltage level indicating, in real time, a first duty cycle length of high voltage duty cycles of the input clock signal. The second output voltage has a second DC voltage level indicating, in real time, a second duty cycle length of low voltage duty cycles of the input clock signal. The difference between the first and second DC voltage levels corresponds to the duty cycle distortion level of the input clock signal. A duty cycle control signal is generated based on the difference between the first and second DC voltage levels to control the high voltage duty cycles of the input clock signal. ## Claims ### Claim 1 A method for controlling duty cycle distortion of clock signals, comprising: obtaining an input clock signal; generating a first periodic signal and a second periodic signal based on a plurality of parallel data and the input clock signal, wherein the first periodic signal is enabled in each high voltage duty cycle of the input clock signal, and the second periodic signal is enabled in each low voltage duty cycle of the input clock signal; generating a first output voltage and a second output voltage based on the first periodic signal and the second periodic signal, wherein: the first output voltage has a first direct current (DC) voltage level indicating, in real time, a first duty cycle length of high voltage duty cycles of the input clock signal; the second output voltage has a second DC voltage level indicating, in real time, a second duty cycle length of low voltage duty cycles of the input clock signal; a difference between the first DC voltage level and the second DC voltage level corresponds to a duty cycle distortion level of the input clock signal; and based on the difference between the first DC voltage level and the second DC voltage level, generating a duty cycle control signal to control the high voltage duty cycles of the input clock signal. ### Claim 2 (depends on 1) The method of claim 1, further comprising: applying a first low-pass filter to filter the first periodic signal and generate the first output voltage; and applying a second low-pass filter to filter the second periodic signal and generate the second output voltage. ### Claim 3 (depends on 1) The method of claim 1, further comprising: amplifying the first output voltage and second output signal by a gain to generate a first amplified voltage and a second amplified voltage, respectively. ### Claim 4 (depends on 3) The method of claim 3, further comprising: dynamically adjusting the gain to control the first amplified voltage and the second amplified voltage in a predefined output dynamic range. ### Claim 5 (depends on 1) The method of claim 1, further comprising: converting the difference between the first DC voltage level and the second DC voltage level to the duty cycle control signal using at least an analog-to-digital converter (ADC). ### Claim 6 (depends on 1) The method of claim 1, wherein the input clock signal corresponds to an inverse clock signal that is substantially complementary to the input clock signal, and the method further comprises: in accordance with a determination that the first DC voltage level is greater than the second DC voltage level by at least a threshold output voltage, implementing at least one of: (i) reducing the high voltage duty cycles of the input clock signal based on the duty cycle control signal and (ii) increasing high voltage duty cycles of the inverse clock signal based on the duty cycle control signal. ### Claim 7 (depends on 1) The method of claim 1, wherein the input clock signal corresponds to an inverse clock signal that is substantially complementary to the input clock signal, and the method further comprises: in accordance with a determination that the second DC voltage level is greater than the first DC voltage level by at least a threshold output voltage, implementing at least one of: (i) increasing the high voltage duty cycles of the input clock signal based on the duty cycle control signal and (ii) decreasing high voltage duty cycles of the inverse clock signal based on the duty cycle control signal. ### Claim 8 (depends on 1) The method of claim 1, wherein the duty cycle control signal includes a multi-bit digital control signal, and the method further comprises: controlling the duty cycles of the input clock signal by selecting a first delay time of a first plurality of delay times for the input clock signal by the multi-bit digital control signal. ### Claim 9 (depends on 8) The method of claim 8, wherein the input clock signal corresponds to an inverse clock signal that is substantially complementary to the input clock signal, and the method further comprises: controlling the duty cycles of the inverse clock signal by selecting a second delay time of a second plurality of delay times for the inverse clock signal by the multi-bit digital control signal. ### Claim 10 (depends on 8) The method of claim 8, wherein the input clock signal is driven by a plurality of parallel buffers, and selecting the first delay time further comprises: selecting a corresponding subset of the plurality of parallel buffers to deliver a drive current that enables the first delay time for the input clock signal. ### Claim 11 (depends on 8) The method of claim 8, wherein the input clock signal is coupled to a plurality of parallel load capacitors, and selecting the first delay time further comprises: selecting and coupling a corresponding subset of the plurality of parallel load capacitors to create a load capacitance that enables the first delay time for the input clock signal. ### Claim 12 (depends on 11) The method of claim 11, wherein: each load capacitor has a first electrode and a second electrode, and is formed from a transistor device having a source, a drain, a gate, and a body; and the gate is coupled to the first electrode, and the source, drain, and body of the transistor device are shorted and coupled to the second electrode. ### Claim 13 (depends on 8) The method of claim 8, wherein the input clock signal is coupled to a plurality of successive buffer stages, each buffer stage including a plurality of parallel buffers and a plurality of parallel load capacitors, and selecting the first delay time further comprises, based on the multi-bit digital control signal: selecting a subset of the plurality of successive buffer stages to be adjusted; for each selected buffer stage, selecting a respective subset of buffers and a respective subset of load capacitors so that the plurality of successive buffer stages enable the first delay time for the input clock signal. ### Claim 14 (depends on 1) The method of claim 1, wherein the duty cycle control signal is generated to control the duty cycle distortion level of the input clock signal to no greater than 1% of a unit interval of the input clock signal. ### Claim 15 An electronic device, comprising: an input circuit unit for generating a first periodic signal and a second periodic signal based on a plurality of parallel data and an input clock signal, wherein the first periodic signal is enabled in each high voltage duty cycle of the input clock signal, and the second periodic signal is enabled in each low voltage duty cycle of the input clock signal; and a module unit coupled to the input circuit unit and including a low pass filter unit, the low pass filter unit configured to generate a first output voltage and a second output voltage based on the first periodic signal and the second periodic signal, wherein: the first output voltage has a first direct current (DC) voltage level indicating a first cycle length of high voltage duty cycles of the input clock signal in real time; the second output voltage has a second DC voltage level indicating a second cycle length of low voltage duty cycles of the input clock signal in real time; a difference between the first and second DC voltage levels corresponds to a duty cycle distortion level of the input clock signal; and the module unit is configured to generate a duty cycle control signal to control the high voltage duty cycle of the input clock signal based on the first and second output voltages. ### Claim 16 (depends on 15) The electronic device of claim 15, further comprising: a first circuit for generating the first periodic signal that is enabled in each high voltage duty cycle of the input clock signal; a second circuit for generating the second periodic signal that is enabled in each low voltage duty cycle of the input clock signal of the input clock signal; a first low-pass filter coupled to the first circuit and configured to filter the first periodic signal and generate the first output voltage; and a second low-pass filter coupled to the second circuit and configured to filter the second periodic signal and generate the second output voltage. ### Claim 17 (depends on 15) The electronic device of claim 15, the module circuit further comprising an amplifier coupled to the low pass filter unit, the amplifier configured to amplify the first output voltage and the second output voltage by a gain to generate a first amplified voltage and a second amplified voltage, respectively. ### Claim 18 (depends on 17) The electronic device of claim 17, wherein the amplifier is configured to dynamically adjust the gain to control the first amplified voltage and the second amplified voltage in a predefined output dynamic range. ### Claim 19 (depends on 15) The electronic device of claim 15, the module unit further comprising at least an analog-to-digital converter (ADC) coupled to the low pass filter unit, the ADC configured to convert the difference between the first DC voltage level and the second DC voltage level to the duty cycle control signal. ### Claim 20 A method for controlling duty cycle distortion of clock signals, comprising: obtaining an input clock signal; generating a first output voltage and a second output voltage, wherein: the first output voltage has a first direct current (DC) voltage level indicating, in real time, a first duty cycle length of high voltage duty cycles of the input clock signal; the second output voltage has a second DC voltage level indicating, in real time, a second duty cycle length of low voltage duty cycles of the input clock signal; a difference between the first DC voltage level and the second DC voltage level corresponds to a duty cycle distortion level of the input clock signal; based on the difference between the first DC voltage level and the second DC voltage level, generating a duty cycle control signal to control the high voltage duty cycles of the input clock signal, wherein the duty cycle control signal includes a multi-bit digital control signal; and controlling the duty cycles of the input clock signal by selecting a first delay time of a first plurality of delay times for the input clock signal by the multi-bit digital control signal.