# US 12,003,240 B1 · Analog memory-based complex multiply-accumulate (MACC) compute engine > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,003,240 B1 - Document ID: US12003240B1 - Status: Granted - Kind: B1 - Application number: 17/978,161 - Filed: 2022-10-31 - Published: 2024-05-16 - Granted: 2024-06-04 - Earliest claimed: 2022-10-31 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Charles Mackin; Pritish Narayanan - Web page: https://patentgrep.com/patent/US12003240B1 ## CPC - G06N 3/065: Analogue means - H03K 3/017: Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor} - G06F 2207/4814: Non-logic devices, e.g. operational amplifiers - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A circuit comprises a first pulse-width modulator configured to generate a first pulse based on a first input, a second pulse-width modulator configured to generate a second pulse based on a second input, a first differential circuit comprising a first transistor, a second transistor, a first resistor, and a second resistor, and a second differential circuit comprising a first transistor, a second transistor, a first resistor, and a second resistor. A gate of the first transistor of the first differential circuit and a gate of the second transistor of the first differential circuit, and a gate of the first transistor of the second differential circuit and a gate of the second transistor of the second differential circuit are configured to be controlled by the first and second pulse width modulators based on the first input and the second input. ## Claims ### Claim 1 A circuit comprising: a first pulse-width modulator configured to generate a first pulse based on a first input; a second pulse-width modulator configured to generate a second pulse based on a second input; a first differential circuit comprising a first transistor, a second transistor, a first resistor, and a second resistor; a second differential circuit comprising a first transistor, a second transistor, a first resistor, and a second resistor, wherein: a gate of the first transistor of the first differential circuit and a gate of the second transistor of the first differential circuit; and a gate of the first transistor of the second differential circuit and a gate of the second transistor of the second differential circuit are configured to be controlled by the first and second pulse width modulators based on the first input and the second input; wherein: the first resistor of the first differential circuit has a configurable resistance, a first terminal of the first resistor is coupled to a voltage supply node and a second terminal of the first resistor is coupled to a first terminal of the first transistor of the first differential circuit; the second resistor of the first differential circuit has a configurable resistance, a first terminal of the second resistor of the first differential circuit is coupled to the voltage via the voltage supply node and a second terminal of the second resistor of the first differential circuit is coupled to a first terminal of the second transistor of the first differential circuit; the first resistor of the second differential circuit has a configurable resistance, a first terminal of the first resistor of the second differential circuit is coupled to the voltage via the voltage supply node and a second terminal of the first resistor of the second differential circuit is coupled to a first terminal of the first transistor of the second differential circuit; and the second resistor of the second differential circuit has a configurable resistance, a first terminal of the second resistor of the second differential circuit is coupled to the voltage via the voltage supply node and a second terminal of the second resistor of the second differential circuit is coupled to a first terminal of the second transistor of the second differential circuit; further comprising an analog-to-digital converter having an input coupled to the voltage supply node. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the first resistor and the second resistor of the first differential circuit are configured based on a first corresponding weight of a multiply-accumulate operation and the first resistor and the second resistor of the second differential circuit are configured based on a second corresponding weight of the multiply-accumulate operation. ### Claim 3 (depends on 1) The circuit of claim 1, further comprising: a first input register coupled to an input of the first pulse-width modulator and configured to store the first input; a second input register coupled to an input of the second pulse-width modulator and configured to store the second input; and a controller circuit configured to control loading of the first input register and the second input register. ### Claim 4 (depends on 1) The circuit of claim 1, further comprising: a real component output register, an input of the real component output register being coupled to an output of the analog-to-digital converter; an imaginary component output register, an input of the imaginary component output register being coupled to the output of the analog-to-digital converter; and a controller circuit configured to control loading of the real component output register and the imaginary component output register. ### Claim 5 (depends on 1) The circuit of claim 1, wherein a second terminal of the first transistor of the first differential circuit, a second terminal of the second transistor of the first differential circuit, a second terminal of the first transistor of the second differential circuit, and a second terminal of the second transistor of the second differential circuit are configured to be selectively coupled between a voltage representing a sign of the first input and a voltage representing a sign of the second input, further comprising a controller circuit configured to control the selective coupling between the voltage representing the sign of the first input and the voltage representing the sign of the second input. ### Claim 6 (depends on 1) The circuit of claim 1, wherein the analog-to-digital converter comprises one or more current mirrors and one or more capacitive elements configured to accumulate charge from the voltage supply node. ### Claim 7 (depends on 1) The circuit of claim 1, wherein the first terminal of the first transistor of the first differential circuit, the first terminal of the second transistor of the first differential circuit, the first terminal of the first transistor of the second differential circuit, the first terminal of the second transistor of the second differential circuit, a second terminal of the first transistor of the first differential circuit, a second terminal of the second transistor of the first differential circuit, a second terminal of the first transistor of the second differential circuit, and a second terminal of the second transistor of the second differential circuit are each a corresponding one of a source terminal and a drain terminal. ### Claim 8 A circuit comprising: a differential circuit comprising a first transistor, a second transistor, a first resistor, and a second resistor; a first pulse-width modulator configured to generate a pulse based on a first input, an output of the first pulse-width modulator configured to be selectively coupled to one of a gate of the first transistor of the differential circuit and a gate of the second transistor of the differential circuit; the first resistor of the differential circuit having a configurable resistance, a first terminal of the first resistor coupled to a voltage supply node and a second terminal of the first resistor coupled to a first terminal of the first transistor; a second pulse-width modulator configured to generate a pulse based on a second input, an output of the second pulse-width modulator configured to be selectively coupled to one of the gate of the first transistor of the differential circuit and the gate of the second transistor of the differential circuit; the second resistor of the differential circuit having a configurable resistance, a second terminal of the second resistor coupled to the voltage via the voltage supply node and coupled to the second terminal of the first resistor, and a second terminal of the second resistor coupled to a first terminal of the second transistor; and an analog-to-digital converter having an input coupled to the voltage supply node. ### Claim 9 (depends on 8) The circuit of claim 8, wherein the first resistor of the first differential circuit is configured based on a first corresponding weight of a multiply-accumulate operation and the second resistor of the first differential circuit is configured based on a second corresponding weight of the multiply-accumulate operation. ### Claim 10 (depends on 8) The circuit of claim 8, further comprising: a first input register coupled to an input of the first pulse-width modulator and configured to store the first input; a second input register coupled to an input of the second pulse-width modulator and configured to store the second input; and a controller circuit configured to control loading of the first input register and the second input register. ### Claim 11 (depends on 8) The circuit of claim 8, further comprising: a real component output register having an input coupled to an output of the analog-to-digital converter; an imaginary component output register having an input coupled to the output of the analog-to-digital converter; and a controller circuit configured to control loading of the real component output register and the imaginary component output register. ### Claim 12 (depends on 8) The circuit of claim 8, wherein a second terminal of the first transistor and a second terminal of the second transistor are configured to be selectively coupled between a voltage input representing a sign bit of the first input and a voltage input representing a sign bit of the second input and further comprising a controller circuit configured to control the selective coupling between the voltage input representing the sign of the first input and the voltage input representing the sign of the second input. ### Claim 13 (depends on 8) The circuit of claim 8, wherein the first terminal of the first transistor, the first terminal of the second transistor of the first differential circuit, a second terminal of the first transistor, and a second terminal of the second transistor are each a corresponding one of a source terminal and a drain terminal. ### Claim 14 (depends on 8) The circuit of claim 8, further comprising: a first shared transistor; a second shared transistor; the first shared resistor having a configurable resistance, a first terminal of the first shared resistor being coupled to the voltage via the voltage supply node and a second terminal of the first shared resistor being coupled to a first terminal of the first shared transistor; the second shared resistor having a configurable resistance, a first terminal of the second shared resistor being coupled to the voltage supply node and a second terminal of the second shared resistor being coupled to a first terminal of the second shared transistor; and a second analog-to-digital converter having an input coupled to the voltage supply node; wherein: the output of the first pulse-width modulator is configured to be selectively coupled to one of a gate of the first shared transistor and a gate of the second shared transistor; and the output of the second pulse-width modulator is configured to be selectively coupled to one of the gate of the first shared transistor and the gate of the second shared transistor. ### Claim 15 (depends on 14) The circuit of claim 14, further comprising: a real component shared output register having an input coupled to an output of the analog-to-digital converter; and an imaginary component shared output register having an input coupled to the output of the analog-to-digital converter. ### Claim 16 (depends on 14) The circuit of claim 14, wherein a second terminal of the first shared transistor and a second terminal of the second shared transistor are configured to be selectively coupled between a voltage input representing a sign bit of the first input and a voltage input representing a sign bit of the second input. ### Claim 17 (depends on 14) The circuit of claim 14, wherein the first terminal of the first shared transistor, the first terminal of the second shared transistor, a second terminal of the first shared transistor, and a second terminal of the second shared transistor are each a corresponding one of a source terminal and a drain terminal.