# US 12,003,238 B2 · Fast memory for programmable devices

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- Number: US 12,003,238 B2
- Document ID: US12003238B2
- Status: Granted
- Kind: B2
- Application number: 17/407,700
- Filed: 2021-08-20
- Published: 2021-12-09
- Granted: 2024-06-04
- Earliest claimed: 2019-01-22
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Scott Jeremy Weber; Aravind Raghavendra Dasu; Mahesh A. Iyer; Patrick Koeberl
- Web page: https://patentgrep.com/patent/US12003238B2

## CPC

- H03K 19/17756: for partial configuration or partial reconfiguration
- H03K 19/17744: {for input/output signals}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/641: {Adaptable interconnections, e.g. fuses or antifuses}
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- H10W 72/01: {Manufacture or treatment}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface.

## Claims

### Claim 1

A system, comprising:
a programmable fabric die having a programmable fabric of programmable elements that is sequentially configured using a sequence of partial reconfiguration personas that define how the programmable elements are configured for one or more portions of the programmable fabric; and
a base die having one or more memory blocks that store a first subset of the partial reconfiguration personas for loading into the fabric die at a future time while a second subset of the partial reconfiguration personas are used to perform an operation in the programmable fabric, wherein loading the partial reconfiguration personas comprises loading the partial reconfiguration personas into the programmable fabric using a first microbump interface of the base die and via a second microbump interface of the fabric die.

### Claim 2 (depends on 1)

The system of claim 1, wherein the sequence comprises a static sequence of the partial reconfiguration personas.

### Claim 3 (depends on 1)

The system of claim 1, wherein the partial reconfiguration personas are aligned to sectors of the programmable fabric.

### Claim 4 (depends on 1)

The system of claim 1, wherein the sequence of the partial reconfiguration personas comprises at least one of the partial reconfiguration personas occurring more than once in the sequence.

### Claim 5 (depends on 1)

The system of claim 1, wherein the partial reconfiguration personas and data are separated in the one or more memory blocks of the base die in a compilation of the partial reconfiguration personas.

### Claim 6 (depends on 1)

The system of claim 1, wherein the sequence comprises a swapped order after a first compilation of the partial reconfiguration personas.

### Claim 7 (depends on 1)

The system of claim 1, wherein the base die is larger extends beyond the fabric die in at least one direction.

### Claim 8 (depends on 1)

The system of claim 1, wherein a partial reconfiguration persona is moved between portions of the fabric die and a memory allocation is moved between sectors of the memory die.

### Claim 9 (depends on 8)

The system of claim 8, wherein the movement in the fabric die and the movement in the base die are performed in parallel.

### Claim 10 (depends on 8)

The system of claim 8, wherein a target portion of the fabric die for the movement in the fabric die and a target sector of the base die for the movement in the base die are corresponding portions and sectors.

### Claim 11

A method, comprising:
loading a plurality of partial reconfiguration personas into a programmable fabric of a fabric die of a programmable logic device, wherein a partial reconfiguration persona is aligned to a corresponding sector of the programmable fabric;
loading a background partial reconfiguration persona into a base die of the programmable logic device while performing operations using the partial reconfiguration persona; and
loading the background partial reconfiguration persona into the programmable fabric from the base die in place of the partial reconfiguration persona, wherein loading the background partial reconfiguration persona into the programmable fabric comprises loading the background partial reconfiguration persona into the programmable fabric using a first microbump interface of the base die, and loading the background partial reconfiguration persona into the programmable fabric comprises loading from the first microbump interface of the base die via a second microbump interface of the fabric die.

### Claim 12 (depends on 11)

The method of claim 11, wherein communications between a partial reconfiguration region loaded with the partial reconfiguration persona comprises pathways around additional partial reconfiguration regions loaded with additional reconfiguration personas in the programmable fabric.

### Claim 13 (depends on 12)

The method of claim 12, wherein the pathways comprise connections through the base die.

### Claim 14 (depends on 13)

The method of claim 13, wherein the connections through the base die comprise a network on chip of the base die.

### Claim 15

A programmable fabric device, comprising:
a fabric die having a programmable fabric comprising:
a plurality of partial reconfiguration regions each corresponding to a design for the programmable fabric, wherein a partial reconfiguration region of the plurality of partial reconfiguration regions is aligned to a corresponding sector of the programmable fabric, wherein the programmable fabric is sequentially configured using a sequence of plurality of partial reconfiguration personas;
an external sector outside of the plurality of partial reconfiguration regions; and
fabric resources that couple the external sector to a sector of the plurality of the partial reconfiguration regions; and
a base die coupled to the external sector and that provides interconnection to the external sectors, wherein the base die has one or more memory blocks that store a first subset of the plurality of partial reconfiguration personas while a second subset of the plurality of partial reconfiguration personas are used to perform an operation in the programmable fabric that have been loaded to the programmable fabric from the base die, wherein loading the second subset of the plurality of partial reconfiguration personas comprises loading the second subset of the plurality of partial reconfiguration personas into the programmable fabric using a first microbump interface of the base die and via a second microbump interface of the fabric die.

### Claim 16 (depends on 15)

The programmable fabric device of claim 15, wherein the external sector enables communications between regions using external paths outside of the plurality of partial reconfiguration regions.

### Claim 17 (depends on 16)

The programmable fabric device of claim 16, wherein communications from the partial reconfiguration region of the plurality of partial reconfiguration regions uses the external sector.

### Claim 18 (depends on 15)

The programmable fabric device of claim 15, wherein communications from the partial reconfiguration regions of the plurality of partial reconfiguration regions uses a network on chip of the base die.